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CSR Bit Fields

RISC-V vstimecmp CSR Register

Address 0x24DPrivilege Hypervisor direct / VS aliasAccess HRW / 64-bitHypervisor and virtualization CSRs

vstimecmp is Sstc's 64-bit VS timer-compare CSR; VSTIP eventually becomes pending when unsigned (time + htimedelta) mod 2^64 is greater than or equal to it.

Related Search Terms
vstimecmp CSRvstimecmp 0x24Dvstimecmp VSTIPvstimecmp htimedeltahenvcfg STCEhcounteren TMvstimecmph high half
Bit Overview
bit 3 = only bit 3; bits 12..11 = bits 12 down to 11
MSBLSB
TIMECMP63:0RW
Field Map

Understand vstimecmp By Bit Fields

1 key fields
63:0

TIMECMP

RW

Unsigned VS timer-compare value with 64-bit precision on every RV32 and RV64 system. On RV32, address 0x24D accesses the low 32 bits and vstimecmph accesses the high 32 bits.

TIMECMP (bits 63:0) — Unsigned VS timer-compare value with 64-bit precision on every RV32 and RV64 system. On RV32, address 0x24D accesses the low 32 bits and vstimecmph accesses the high 32 bits.

What This Field Controls

  • - Unsigned VS timer-compare value with 64-bit precision on every RV32 and RV64 system. On RV32, address 0x24D accesses the low 32 bits and vstimecmph accesses the high 32 bits.

Common Values

This field is better understood together with surrounding context than as a fixed memorized enumeration.

↗Open Official Manual
Official Basis & Search Notes

vstimecmp holds a guest's 64-bit timer deadline. hip.VSTIP eventually sets when unsigned (time + htimedelta) mod 2^64 reaches it.

vstimecmp address, access class, and width are checked against the official CSR tables: 0x24D, HRW, 64-bit.
Sstc with H adds VS-level vstimecmp; mcounteren.TM gates direct HS access, while VS alias access through stimecmp must also pass the menvcfg.STCE, henvcfg.STCE, and hcounteren.TM gates.
The state has 64-bit precision on RV32 and RV64; RV32 accesses the low and high halves through vstimecmp and vstimecmph.
The comparison result is reflected in VSTIP eventually but not necessarily immediately; delivery follows standard enable and delegation rules. With AIA, hvictl.VTI=1 intercepts VS-mode writes to stimecmp/stimecmph.
RISC-V Privileged Architecture Manual - CSR tableRISC-V Privileged Architecture Manual - Hypervisor extensionRISC-V Sstc extensionRISC-V Advanced Interrupt Architecture - VS-level interrupts

What To Check First When Reading This CSR

  • - vstimecmp's separate CSR address is in the official HRW access class; a VS/VU guest normally reaches VS state through the corresponding supervisor CSR alias.
  • - vstimecmp is defined only with Sstc and H. For VS-mode alias access through stimecmp, menvcfg.STCE, mcounteren.TM, henvcfg.STCE, and hcounteren.TM must all permit access.

Risk Checks Before Writing

  • - After writing vstimecmp, the VSTIP change is eventually visible but need not be immediate; software must tolerate a brief spurious timer interrupt after advancing the deadline.
  • - With AIA and hvictl.VTI=1, a VS-mode write to stimecmp (and to stimecmph on RV32) raises a virtual-instruction exception because the write may clear vsip.STIP.

Put It Back Into A Real Flow

1

Confirm Sstc/H. Direct HS access to vstimecmp is gated by mcounteren.TM; VS guest alias access through stimecmp additionally requires menvcfg.STCE, henvcfg.STCE, and hcounteren.TM.

2

Write the deadline as unsigned 64-bit state; RV32 updates the low and high halves through vstimecmp and vstimecmph respectively.

3

The comparison uses time + htimedelta truncated to 64 bits; interrupt delivery still follows standard enable and delegation rules.

FAQ

Is vstimecmp part of 64-bit timer state?

vstimecmp represents a 64-bit VS timer compare value; RV32 uses the matching high-half CSR.

How is vstimecmp related to time?

Hardware compares vstimecmp with unsigned (time + htimedelta) mod 2^64; VSTIP eventually sets when the latter is greater than or equal to the former.