AMOCAS.D

RISC-V AMOCAS.D Instruction Details

Instruction ManualR-type

Atomic compare-and-swap doubleword: compare memory with rd/register pair, store rs2/register pair on match, return old value in rd

Instruction Syntax

amocas.d rd, rs2, (rs1)
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
ZacasAtomic Operation

Instruction Behavior

AMOCAS.D (Zacas extension) atomically loads a 64-bit doubleword from the address in rs1 and compares it with the compare operand; on a match it stores the swap operand. On RV64, the compare value is rd, the swap value is rs2, and the old value is written to rd. On RV32, the compare value is the even rd/rd+1 register pair, the swap value is the even rs2/rs2+1 pair, and the old value is written to rd/rd+1; odd rd or rs2 encodings are reserved. aq/rl ordering bits are supported.

AMOCAS.D Atomic Decode And Execute Animation

Shows Zacas doubleword atomic field decode, aq/rl ordering bits, memory read, and CAS state update.

rd
rs2
rs1
amocas.d
,
,(
)
Execution Context
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00101
funct5
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aq
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rl
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rs1
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funct3
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rd
0101111
opcode
Atomic Data Path
instruction
0x2CC5B52F
opcode
0101111 -> AMO
funct3
011 -> doubleword width
funct5
00101 -> AMOCAS.D
aq / rl
1/0 -> acquire
rd / rs2 / rs1
a0(x10)/a1(x11) compare=0x8000000000000002 / a2(x12)/a3(x13) swap=0x000000000000007F / a1(x11)=0x00001000
memory read
mem[0x00001000] -> old doubleword 0x8000000000000002
RMW
0x8000000000000002 == 0x8000000000000002 -> store 0x000000000000007F
rd / memory
a0(x10)/a1(x11) = old doubleword 0x8000000000000002; mem[0x00001000] = 0x000000000000007F
Current Step

Concept Step: receive the 32-bit atomic instruction encoding

Zacas-extension doubleword atomic instructions use a 32-bit encoding; the animation starts by splitting the fields.

encoding: 0x2CC5B52F
syntax : amocas.d a0(x10), a2(x12), (a1(x11))
result : a0(x10)/a1(x11) = old doubleword 0x8000000000000002; mem[0x00001000] = 0x000000000000007F
64-bit Doubleword Result View
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This animation shows ISA-visible atomic read-modify-write, compare-and-swap, LR/SC reservation state, and ordering bits, not any specific CPU cache-coherence implementation, pipeline, or timing.

Quick Understanding & Search Notes

AMOCAS.D atomically loads a 64-bit memory value and compares it bitwise with the compare operand; on equality it stores the swap operand. RV64 uses rd/rs2, RV32 uses the rd/rd+1 and rs2/rs2+1 register pairs, and the old memory value is always returned.

Before execution rd supplies the compare value; after execution rd is overwritten by the old memory value, not a Boolean success flag.
On RV32, AMOCAS.D uses even-numbered register pairs; on RV64 it uses a single 64-bit register.
The address must be naturally aligned to the operand size; aq/rl ordering on success and failure follows the Zacas rules.

Common Usage Scenarios

Atomic & Sync

Understand this scenario with real code like «amocas.d a0, a2, (a1)».

Network & Byte Order

Understand this scenario with real code like «amocas.d a0, a2, (a1)».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is R-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

AMOCAS.D is not RV64-only; RV32 uses even/odd register pairs.
The compare value comes from rd (or rd/rd+1 on RV32), not rs2; rs2 is the new value stored on success.
rd returns the old memory value, not a success flag; the target address must be naturally 8-byte aligned unless relaxed by PMA.

FAQ

How do I tell whether AMOCAS.D succeeded?

On RV64, compare the old value returned in rd with the expected value; on RV32, compare the complete 64-bit old value returned in rd/rd+1. Equality indicates that the swap store occurred.

Does AMOCAS.D take the compare value from rs2?

No. rs2 supplies the new value to store on success; the compare value comes from rd before execution, or from the rd register pair.