Atomic 64-bit compare-and-swap: RV64 uses rd/rs2; RV32 uses even register pairs. Return old memory and replace it on a match
Syntax is rd, rs2, (rs1), with no offset or rs3. Pre-execution rd supplies the comparison, rs2 the replacement, and rs1 the address.
32-bit encoding: funct5=00101, funct3=011, opcode=0101111; aq is bit26 and rl is bit25.
RV32/RV64, requiring Zacas (which depends on Zaamo). Compare 64-bit old memory and replace on equality; normal completion returns old memory, not a Boolean flag.
RV32 uses even rd/rd+1 and rs2/rs2+1 pairs, low half first. Odd starting registers are reserved; x0 sources supply an all-zero pair and x0 destinations discard both writes. RV64 uses single rd/rs2 registers.
Use 8-byte alignment, or a PMA with all accessed bytes in one misaligned atomicity granule; otherwise address-misaligned or access-fault is raised. The region must support this AMOCAS; overlapping registers read one pre-execution value, and aq/rl orders only the accessed domain.
AMOCAS.D (Zacas extension) atomically loads a 64-bit doubleword from the address in rs1 and compares it with the compare operand; on a match it stores the swap operand. On RV64, the compare value is rd, the swap value is rs2, and the old value is written to rd. On RV32, even rd is the low 32-bit half of the compare pair and rd+1 the high half; even rs2 is the low 32-bit half of the swap pair and rs2+1 the high half, and the old value is returned to rd/rd+1 in that order. Odd rd or rs2 encodings are reserved. When a source pair starts at x0, both halves read as zero; when the rd pair starts at x0, the entire result is discarded. aq/rl ordering bits are supported. These data results assume normal completion of the access; rd=x0 discards writeback. Zacas depends on Zaamo.
Shows Zacas doubleword atomic field decode, aq/rl ordering bits, a memory read, and CAS state update.
Zacas-extension doubleword atomic instructions use a 32-bit encoding; the animation starts by splitting the fields.
Assumes enabled extensions at the selected XLEN, successful fetch, and a region supporting this AMOCAS with successful access; W/D/Q can select a missing-write-permission exception path. Misalignment requires the stated PMA condition. Sources are read before writeback; x0 sources are zero (both halves for a pair). aq/rl orders only the accessed domain. Steps are a teaching sequence.
AMOCAS.D atomically loads a 64-bit memory value and compares it bitwise with the compare operand; on equality it stores the swap operand. RV64 uses rd/rs2, RV32 uses the rd/rd+1 and rs2/rs2+1 register pairs, and normal completion returns the old value (discarding writeback for rd=x0).
RV32/RV64 with required extensions enabled; assume a4=0x1000 and a supporting region with normal completion. With old memory=5, expected=5 and replacement=3, the example returns 5 and stores 3; changing expected to 4 returns 5 and leaves memory data at 5. Pair forms use a0/a1 and a2/a3 as complete values; this example holds the address in a4 to avoid overlap.
After normal completion with nonzero rd, compare the returned old memory value with the expected value saved before execution: use rd on RV64, or the complete 64-bit rd/rd+1 value on RV32. Equality indicates that the swap store occurred.
No. RV64 compares rd and replaces from rs2; RV32 compares the even rd/rd+1 pair and replaces from the even rs2/rs2+1 pair.