Atomic compare-and-swap halfword: compare memory with rd[15:0], store rs2[15:0] on match, return old value in rd
Syntax is rd, rs2, (rs1), with no offset or rs3. Pre-execution rd supplies the comparison, rs2 the replacement, and rs1 the address.
32-bit encoding: funct5=00101, funct3=001, opcode=0101111; aq is bit26 and rl is bit25.
RV32/RV64, requiring Zacas (which depends on Zaamo) and Zabha. Compare 16-bit old memory and replace on equality; normal completion returns old memory, not a Boolean flag.
Use only the low 16 rd/rs2 bits for comparison/replacement; sign-extend old memory to XLEN. x0 sources are zero and x0 destination writes are discarded.
Use 2-byte alignment, or a PMA with all accessed bytes in one misaligned atomicity granule; otherwise address-misaligned or access-fault is raised. The region must support this AMOCAS; overlapping registers read one pre-execution value, and aq/rl orders only the accessed domain.
AMOCAS.H (the halfword AMOCAS form provided by Zabha, with Zacas CAS semantics) atomically loads a 16-bit value from the address in rs1 and compares it with the low 16 bits of rd; on a bitwise match it stores the low 16 bits of rs2 back to the same address. The loaded old value is sign-extended to XLEN and written to rd regardless of success. aq/rl ordering bits are supported. These data results assume normal completion of the access; rd=x0 discards writeback. Zacas depends on Zaamo.
Shows Zabha + Zacas halfword atomic field decode, aq/rl ordering bits, a memory read, and CAS state update.
Zabha + Zacas-extension halfword atomic instructions use a 32-bit encoding; the animation starts by splitting the fields.
Assumes enabled extensions at the selected XLEN, successful fetch, and a region supporting this AMOCAS with successful access; W/D/Q can select a missing-write-permission exception path. Misalignment requires the stated PMA condition. Sources are read before writeback; x0 sources are zero (both halves for a pair). aq/rl orders only the accessed domain. Steps are a teaching sequence.
AMOCAS.H atomically loads a 16-bit memory value, compares it bitwise with the compare value supplied in rd, stores the rs2 swap value on equality, and on normal completion returns the old value in rd (discarding the write for rd=x0).
RV32/RV64 with required extensions enabled; assume a1=0x1000 and a supporting region with normal completion. With old memory=5, expected=5 and replacement=3, the example returns 5 and stores 3; changing expected to 4 returns 5 and leaves memory data at 5.
After normal completion with nonzero rd, compare the low 16 bits of the value returned in rd with the low 16 bits of the expected value saved before execution; equality indicates that the swap store occurred. The returned halfword is sign-extended in rd.
No. The low operand-width bits of rd before execution supply the compare value; the same-width low bits of rs2 supply the replacement.