How do I tell whether AMOCAS.Q succeeded?
After normal completion with nonzero rd, compare the old memory value returned in rd/rd+1 with the complete 128-bit expected value saved before execution; equality indicates that the swap store occurred.
RV64 atomic compare-and-swap quadword: compare 128-bit rd/rd+1, store rs2/rs2+1 on match, return old value in rd/rd+1
Syntax is rd, rs2, (rs1), with no offset or rs3. Pre-execution rd supplies the comparison, rs2 the replacement, and rs1 the address.
32-bit encoding: funct5=00101, funct3=100, opcode=0101111; aq is bit26 and rl is bit25.
RV64 only, requiring Zacas (which depends on Zaamo). Compare 128-bit old memory and replace on equality; normal completion returns old memory, not a Boolean flag.
RV64 uses even rd/rd+1 and rs2/rs2+1 pairs, low half first. Odd starting registers are reserved; x0 sources supply an all-zero pair and x0 destinations discard both writes.
Use 16-byte alignment, or a PMA with all accessed bytes in one misaligned atomicity granule; otherwise address-misaligned or access-fault is raised. The region must support this AMOCAS; overlapping registers read one pre-execution value, and aq/rl orders only the accessed domain.
AMOCAS.Q (Zacas extension) is defined only for RV64. It atomically loads a 128-bit quadword from the address in rs1 and bitwise-compares it with the 128-bit compare value in even rd (low 64 bits) and rd+1 (high 64 bits); on a match it stores the 128-bit swap value from even rs2 (low 64 bits) and rs2+1 (high 64 bits). The old memory value is written back to rd/rd+1 in the same order. rd and rs2 must be even; odd encodings are reserved. When a source pair starts at x0, both halves read as zero; when the rd pair starts at x0, the entire result is discarded. aq/rl ordering bits are supported. These data results assume normal completion of the access; rd=x0 discards writeback. Zacas depends on Zaamo.
Shows Zacas quadword atomic field decode, aq/rl ordering bits, a memory read, and CAS state update.
Zacas-extension quadword atomic instructions use a 32-bit encoding; the animation starts by splitting the fields.
Assumes enabled extensions at the selected XLEN, successful fetch, and a region supporting this AMOCAS with successful access; W/D/Q can select a missing-write-permission exception path. Misalignment requires the stated PMA condition. Sources are read before writeback; x0 sources are zero (both halves for a pair). aq/rl orders only the accessed domain. Steps are a teaching sequence.
AMOCAS.Q atomically loads a 128-bit memory value, compares it bitwise with the compare value supplied in the rd/rd+1 register pair, stores the rs2/rs2+1 swap value on equality, and on normal completion returns the old value in rd/rd+1 (discarding both writes for rd=x0).
RV64 with required extensions enabled; assume a4=0x1000 and a supporting region with normal completion. With old memory=5, expected=5 and replacement=3, the example returns 5 and stores 3; changing expected to 4 returns 5 and leaves memory data at 5. Pair forms use a0/a1 and a2/a3 as complete values; this example holds the address in a4 to avoid overlap.
After normal completion with nonzero rd, compare the old memory value returned in rd/rd+1 with the complete 128-bit expected value saved before execution; equality indicates that the swap store occurred.
No. The full 128-bit comparison comes from the even rd/rd+1 pair before execution; the even rs2/rs2+1 pair supplies the full 128-bit replacement.