Home/Instructions/AMOCAS-Q

AMOCAS.Q

RISC-V AMOCAS.Q Instruction Details

Instruction ManualR-type

RV64 atomic compare-and-swap quadword: compare 128-bit rd/rd+1, store rs2/rs2+1 on match, return old value in rd/rd+1

Instruction Syntax

amocas.q rd, rs2, (rs1)

Operand Breakdown

Destination rd: register receiving the operation result.

Source rs1: register holding the first operand.

Source rs2: register holding the second operand.

ZacasAtomic Operation

Related Search Terms

amocas.q instruction RISC-V amocas.q quadword CAS Zacas amocas.q amocas.q encoding amocas.q compare value amocas.q register pair

Instruction Behavior

AMOCAS.Q (Zacas extension) is defined only for RV64. It atomically loads a 128-bit quadword from the address in rs1 and bitwise-compares it with the 128-bit compare value in the even rd/rd+1 pair; on a match it stores the 128-bit swap value from the even rs2/rs2+1 pair. The old memory value is written back to rd/rd+1. rd and rs2 must be even; odd encodings are reserved. aq/rl ordering bits are supported.

AMOCAS.Q Atomic Decode And Execute Animation

Shows Zacas quadword atomic field decode, aq/rl ordering bits, memory read, and CAS state update.

rs2

rs1

amocas.q

)

Execution ContextXLENmemory addressold memory quadwordrd compare quadwordrs2 quadwordaqrl

31..27

24..20

19..15

14..12

11..7

6..0

00101

funct5

01100

rs2

01011

rs1

100

funct3

01010

0101111

opcode

Atomic Data Path

instruction

0x2CC5C52F

opcode

0101111 -> AMO

funct3

100 -> quadword width

funct5

00101 -> AMOCAS.Q

aq / rl

1/0 -> acquire

rd / rs2 / rs1

a0(x10)/a1(x11) compare=0x00000000000000010000000000000002 / a2(x12)/a3(x13) swap=0x0000000000000000000000000000007F / a1(x11)=0x0000000000001000

memory read

mem[0x0000000000001000] -> old quadword 0x00000000000000010000000000000002

RMW

0x00000000000000010000000000000002 == 0x00000000000000010000000000000002 -> store 0x0000000000000000000000000000007F

rd / memory

a0(x10)/a1(x11) = old quadword 0x00000000000000010000000000000002; mem[0x0000000000001000] = 0x0000000000000000000000000000007F

Current Step

Concept Step: receive the 32-bit atomic instruction encoding

Zacas-extension quadword atomic instructions use a 32-bit encoding; the animation starts by splitting the fields.

encoding: 0x2CC5C52F

syntax : amocas.q a0(x10), a2(x12), (a1(x11))

result : a0(x10)/a1(x11) = old quadword 0x00000000000000010000000000000002; mem[0x0000000000001000] = 0x0000000000000000000000000000007F

128-bit Quadword Result View

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

CAS match

This animation shows ISA-visible atomic read-modify-write, compare-and-swap, LR/SC reservation state, and ordering bits, not any specific CPU cache-coherence implementation, pipeline, or timing.

Quick Understanding & Search Notes

AMOCAS.Q atomically loads a 128-bit memory value, compares it bitwise with the compare value supplied in the rd/rd+1 register pair, stores the rs2/rs2+1 swap value on equality, and always writes the old memory value back to rd/rd+1.

Before execution rd supplies the compare value; after execution rd is overwritten by the old memory value, not a Boolean success flag.

AMOCAS.Q is the RV64-only 128-bit CAS form and uses even-numbered rd/rs2 register pairs.

The address must be naturally aligned to the operand size; aq/rl ordering on success and failure follows the Zacas rules.

RISC-V Unprivileged ISA Manual: Zacas atomic compare-and-swap extension

Common Usage Scenarios

Atomic & Sync

Understand this scenario with real code like «amocas.q a0, a2, (a1)».

Network & Byte Order

Understand this scenario with real code like «amocas.q a0, a2, (a1)».

Pre-Use Checklist

Syntax Check

Confirm the current instruction format is R-type.
Confirm the operand order matches the example.

Semantic Check

Ensure the destination register usage is compatible with the calling convention.
Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

AMOCAS.Q is an RV64-only 128-bit CAS, not an RV128 instruction.

The compare value comes from rd/rd+1; rs2/rs2+1 is the new value stored on success.

rd and rs2 must be even; the target address must be naturally 16-byte aligned unless relaxed by PMA.

FAQ

How do I tell whether AMOCAS.Q succeeded?

Compare the old value returned in rd/rd+1 with the complete 128-bit expected value; equality indicates that the swap store occurred.

Does AMOCAS.Q take the compare value from rs2?

No. rs2 supplies the new value to store on success; the compare value comes from rd before execution, or from the rd register pair.