AMOCAS.Q

RISC-V AMOCAS.Q Instruction Details

Instruction ManualAMO-type

RV64 atomic compare-and-swap quadword: compare 128-bit rd/rd+1, store rs2/rs2+1 on match, return old value in rd/rd+1

Instruction Syntax

amocas.q rd, rs2, (rs1)

Syntax is rd, rs2, (rs1), with no offset or rs3. Pre-execution rd supplies the comparison, rs2 the replacement, and rs1 the address.

32-bit encoding: funct5=00101, funct3=100, opcode=0101111; aq is bit26 and rl is bit25.

RV64 only, requiring Zacas (which depends on Zaamo). Compare 128-bit old memory and replace on equality; normal completion returns old memory, not a Boolean flag.

RV64 uses even rd/rd+1 and rs2/rs2+1 pairs, low half first. Odd starting registers are reserved; x0 sources supply an all-zero pair and x0 destinations discard both writes.

Use 16-byte alignment, or a PMA with all accessed bytes in one misaligned atomicity granule; otherwise address-misaligned or access-fault is raised. The region must support this AMOCAS; overlapping registers read one pre-execution value, and aq/rl orders only the accessed domain.

ZacasAtomic Operation

Instruction Behavior

AMOCAS.Q (Zacas extension) is defined only for RV64. It atomically loads a 128-bit quadword from the address in rs1 and bitwise-compares it with the 128-bit compare value in even rd (low 64 bits) and rd+1 (high 64 bits); on a match it stores the 128-bit swap value from even rs2 (low 64 bits) and rs2+1 (high 64 bits). The old memory value is written back to rd/rd+1 in the same order. rd and rs2 must be even; odd encodings are reserved. When a source pair starts at x0, both halves read as zero; when the rd pair starts at x0, the entire result is discarded. aq/rl ordering bits are supported. These data results assume normal completion of the access; rd=x0 discards writeback. Zacas depends on Zaamo.

AMOCAS.Q Atomic Decode And Execute Animation

Shows Zacas quadword atomic field decode, aq/rl ordering bits, a memory read, and CAS state update.

rd/rd+1
rs2/rs2+1
rs1
amocas.q
,
,(
)
Execution Context
31..27
26
25
24..20
19..15
14..12
11..7
6..0
00101
funct5
1
aq
0
rl
01100
rs2
01110
rs1
100
funct3
01010
rd
0101111
opcode
Atomic Data Path
instruction
0x2CC7452F
opcode
0101111 -> AMO
funct3
100 -> quadword width
funct5
00101 -> AMOCAS.Q
aq / rl
1/0 -> acquire
write permission
permitted: CAS may proceed
rd / rs2 / rs1
a0(x10) (low)/a1(x11) (high) compare=0x00000000000000010000000000000002 / a2(x12) (low)/a3(x13) (high) swap=0x0000000000000000000000000000007F / a4(x14)=0x0000000000001000
memory read
mem[0x0000000000001000] -> old quadword 0x00000000000000010000000000000002
RMW
Not computed
rd / memory
a0(x10) (low)/a1(x11) (high) = 0x00000000000000010000000000000002; mem[0x0000000000001000] = 0x00000000000000010000000000000002
Current Step

Concept Step: receive the 32-bit atomic instruction encoding

Zacas-extension quadword atomic instructions use a 32-bit encoding; the animation starts by splitting the fields.

encoding: 0x2CC7452F
syntax : amocas.q.aq a0(x10), a2(x12), (a4(x14))
Pending result : Not computed
Current architectural state
a0(x10) (low)/a1(x11) (high) = 0x00000000000000010000000000000002; mem[0x0000000000001000] = 0x00000000000000010000000000000002

Assumes enabled extensions at the selected XLEN, successful fetch, and a region supporting this AMOCAS with successful access; W/D/Q can select a missing-write-permission exception path. Misalignment requires the stated PMA condition. Sources are read before writeback; x0 sources are zero (both halves for a pair). aq/rl orders only the accessed domain. Steps are a teaching sequence.

Quick Understanding & Search Notes

AMOCAS.Q atomically loads a 128-bit memory value, compares it bitwise with the compare value supplied in the rd/rd+1 register pair, stores the rs2/rs2+1 swap value on equality, and on normal completion returns the old value in rd/rd+1 (discarding both writes for rd=x0).

After normal completion with nonzero rd, old memory overwrites the compare operand rd (rd/rd+1 for pair forms), not a Boolean success flag.
AMOCAS.Q is the RV64-only 128-bit CAS form and uses even-numbered rd/rs2 register pairs.
AMOCAS.W/D/Q requires write permission even on comparison failure. aq=1 supplies acquire on success or failure; rl=1 supplies release only on success. Failure may omit a write or write back the old value, without release.

Common Usage Scenarios

Atomic & Sync

RV64 with required extensions enabled; assume a4=0x1000 and a supporting region with normal completion. With old memory=5, expected=5 and replacement=3, the example returns 5 and stores 3; changing expected to 4 returns 5 and leaves memory data at 5. Pair forms use a0/a1 and a2/a3 as complete values; this example holds the address in a4 to avoid overlap.

Pre-Use Checklist

Syntax Check
  • Syntax is rd, rs2, (rs1), with no offset or rs3. Pre-execution rd supplies the comparison, rs2 the replacement, and rs1 the address.
  • 32-bit encoding: funct5=00101, funct3=100, opcode=0101111; aq is bit26 and rl is bit25.
Semantic Check
  • RV64 only, requiring Zacas (which depends on Zaamo). Compare 128-bit old memory and replace on equality; normal completion returns old memory, not a Boolean flag.
  • RV64 uses even rd/rd+1 and rs2/rs2+1 pairs, low half first. Odd starting registers are reserved; x0 sources supply an all-zero pair and x0 destinations discard both writes.
  • Use 16-byte alignment, or a PMA with all accessed bytes in one misaligned atomicity granule; otherwise address-misaligned or access-fault is raised. The region must support this AMOCAS; overlapping registers read one pre-execution value, and aq/rl orders only the accessed domain.

Pitfalls / Common Confusions

AMOCAS.Q is an RV64-only 128-bit CAS, not an RV128 instruction.
The compare value comes from rd/rd+1; rs2/rs2+1 is the new value stored on success.
rd and rs2 must be even; the target address must be naturally 16-byte aligned unless relaxed by PMA.

FAQ

How do I tell whether AMOCAS.Q succeeded?

After normal completion with nonzero rd, compare the old memory value returned in rd/rd+1 with the complete 128-bit expected value saved before execution; equality indicates that the swap store occurred.

Does AMOCAS.Q take the compare value from rs2?

No. The full 128-bit comparison comes from the even rd/rd+1 pair before execution; the even rs2/rs2+1 pair supplies the full 128-bit replacement.