Why does c.andi have register restrictions?
Many C formats encode registers with shorter fields, so some forms can access only x8..x15 or fixed registers.
C.ANDI
RISC-V C.ANDI Instruction Details
Instruction ManualC-typeBitwise AND of rd' with sign-extended 6-bit imm. CB format.
Instruction Syntax
c.andi rd', imm
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
CCompressed Instruction
Instruction Behavior
c.andi ANDs rd' with a sign-extended 6-bit immediate and writes rd'.
Quick Understanding & Search Notes
c.andi ANDs rd' with a sign-extended 6-bit immediate and writes rd'.
Compressed instructions usually mirror a 32-bit base instruction semantic, but with register-subset, immediate-encoding, or XLEN restrictions.
The immediate is sign-extended, not zero-extended.
rd' uses the compressed register subset x8..x15.
Common Usage Scenarios
Bit Operations & Masks
Understand this scenario with real code like «c.andi x8, 0xF # x8 &= 0xF».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is C-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
The immediate is sign-extended, not zero-extended.
rd' uses the compressed register subset x8..x15.
FAQ
Is c.andi just an assembler pseudo-instruction?
No. It is a 16-bit encoded instruction defined by the C extension.