Why does c.andi have register restrictions?
Many C formats encode registers with shorter fields, so some forms can access only x8..x15 or fixed registers.
C.ANDI
RISC-V C.ANDI Instruction Details
Instruction ManualCB-formatBitwise AND of rd' with sign-extended 6-bit imm. CB format.
Instruction Syntax
c.andi rd', imm
rd′ selects x8–x15 and is both the old source and the writeback destination; read the old value before writing.
imm is a signed 6-bit immediate from -32 through 31, sign-extended to XLEN.
RV32C/RV64C: compute x[rd′] AND sext(imm) across XLEN bits and write rd′.
CCompressed Instruction
Instruction Behavior
A 16-bit RV32C/RV64C CB instruction: AND x[rd'] with a 6-bit immediate sign-extended to XLEN and write rd'. rd' is x8–x15; imm is -32–31.
C.ANDI Decode & Execute Animation
Shows only manual-defined 16-bit fields, operands, and ISA-visible results; it does not model a pipeline, cache, timing, or an implementation's memory-fault handling.
c.andi,
Execution context
Scope: RV32C/RV64C, 16-bit CB encoding.
x8 = 0x0000000000001234; imm = -16 -> 0x0000000000001234 AND sext(imm[5:0]=-16) = 0x0000000000001230 -> x8 = 0x0000000000001230
16-bit encoding fields
rd'=000 -> x8; imm[5:0]=110000 -> sext(-16)
15..13
funct3
100
12
imm[5]
1
11..10
funct2
10
9..7
rd'/rs1'
000
6..2
imm[4:0]
10000
1..0
op
01
Execution data path
x8 = 0x0000000000001234; imm = -16
0x0000000000001234 AND sext(imm[5:0]=-16) = 0x0000000000001230
x8 <- 0x0000000000001230
Architectural state has not been committed.
Quick Understanding & Search Notes
A 16-bit RV32C/RV64C CB instruction: AND x[rd'] with a 6-bit immediate sign-extended to XLEN and write rd'. rd' is x8–x15; imm is -32–31.
C.ANDI is a real 16-bit encoding with ANDI semantics; the destination also supplies the old first source value.
The immediate is sign-extended, not zero-extended.
rd' uses the compressed register subset x8..x15.
Common Usage Scenarios
Bit Operations & Masks
RV32C/RV64C, old x8=0x1234: c.andi x8, 0xF writes x8=0x4; 0xF is the legal signed 6-bit immediate 15.
Pre-Use Checklist
Syntax Check
- rd′ selects x8–x15 and is both the old source and the writeback destination; read the old value before writing.
- imm is a signed 6-bit immediate from -32 through 31, sign-extended to XLEN.
Semantic Check
- RV32C/RV64C: compute x[rd′] AND sext(imm) across XLEN bits and write rd′.
Pitfalls / Common Confusions
The immediate is sign-extended, not zero-extended.
rd' uses the compressed register subset x8..x15.
FAQ
Is c.andi just an assembler pseudo-instruction?
No. It is a 16-bit encoded instruction defined by the C extension.