Does C.BEQZ write a return address?
No; it writes no link register. When the condition is true, PC updates to the target; otherwise execution continues at pc+2.
C.BEQZ
RISC-V C.BEQZ Instruction Details
Instruction ManualC-typeBranch if x[rs1'] is zero; otherwise PC+2. 16-bit CB format.
Instruction Syntax
c.beqz rs1', offset
Operand Breakdown
16-bit CB format; the 3-bit rs1' selects x8-x15 and the other comparison operand is fixed to x0.
offset is an even byte displacement from -256 through 254, sign-extended and added to the current instruction PC; zero is legal.
C.BEQZ branches when the register is zero; otherwise PC+2. There is no rd or link write.
CCompressed Instruction
Extension condition: RV32C / RV64C; this page describes C extension version 2.0.
Instruction Behavior
C.BEQZ uses the 16-bit CB format; its 3-bit rs1' selects x8-x15. If the register is zero, the target is the current instruction PC plus a sign-extended byte offset; otherwise execution continues at PC+2. The offset is even, from -256 through 254, including zero. It corresponds to beq rs1', x0, offset and writes no link register.
C.BEQZ Instruction Animation
Three learning stages illustrate architectural rules, without modeling processor pipelines or cycles.
c.beqz,
Execution context
RV32C / RV64C; C sets IALIGN=16, so PC is an even byte address. Address arithmetic wraps at XLEN. Subsequent target instruction-fetch exceptions are outside this model.
c.beqz → Condition true; PC ← 0x00001020; no link register write
16-bit encoding fields
0xC005
15..13
funct3
110
12
offset[8]
0
11..10
offset[4:3]
00
9..7
rs1'
000
6..5
offset[7:6]
00
4..3
offset[2:1]
00
2
offset[5]
1
1..0
op
01
Operands and calculation
Restore compressed operands
rs1'=000 → x8; rs2=x0=0; offset[8]=0; offset[4:3]=00; offset[7:6]=00; offset[2:1]=00; offset[5]=1; imm=000100000; sext(000100000) = 32 B; imm[0]=0; input offset is already in bytes, with no additional scaling.
Calculate
Not computed
Commit result
Pending commit
Architectural result
Architectural result not committed yet.
Quick Understanding & Search Notes
C.BEQZ uses CB format, compares restricted rs1' with implicit x0, and adds a sign-extended offset to PC when the condition is true.
rs1' can encode only x8-x15.
With the C extension, IALIGN=16, so a CB offset in 2-byte multiples satisfies instruction alignment.
Common Usage Scenarios
Conditional branch against zero
Understand this scenario with real code like «c.beqz x8, 32 # PC=0x1000: x8=0 -> PC=0x1020; x8!=0 -> PC=0x1002».
Pre-Use Checklist
Syntax Check
- Confirm RV32C / RV64C and the 16-bit encoding conditions.
- 16-bit CB format; the 3-bit rs1' selects x8-x15 and the other comparison operand is fixed to x0.
Semantic Check
- offset is an even byte displacement from -256 through 254, sign-extended and added to the current instruction PC; zero is legal.
- C.BEQZ branches when the register is zero; otherwise PC+2. There is no rd or link write.
Pitfalls / Common Confusions
Source register limited to x8-x15 (CB format)
The second comparison operand is implicit x0; this instruction has no destination register
The byte offset must be even, from -256 through 254; bit 0 is implicit zero and the target is relative to this instruction PC.