Does C.BEQZ write a return address?
No; it writes no link register. When the condition is true, PC updates to the target; otherwise execution continues at pc+2.
C.BEQZ
RISC-V C.BEQZ Instruction Details
Instruction ManualC-typeBranch if rs1'==0 (±256B). CB format.
Instruction Syntax
c.beqz rs1', offset
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
CCompressed Instruction
Instruction Behavior
C.BEQZ (CB format, rs1' x8-x15 only) branches if rs1' equals zero. Sign-extended offset added to pc, ±256 B range. Expands to beq rs1',x0,offset.
C.BEQZ Decode & Execute Animation
This interactive model shows only architectural decode, operands, and state changes, not a pipeline, cache, or timing model.
c.beqz,
Execution context
Encoding fields
15..13
funct3
110
12
offset[8]
0
11..10
offset[4:3]
00
9..7
rs1'
000
6..5
offset[7:6]
00
4..3
offset[2:1]
00
2
offset[5]
1
1..0
op
01
Execution data path
Decode
CB: rs1' / permuted offset
Operands
x8 = 0x00000000, x0 = 0
Execute
comparison true, choose target
State
PC <- 0x00001020
The zero-comparison condition is true.
Architectural result
Awaiting state update: the highlighted fields and calculation above show the current step; no architectural result has been committed yet.
Quick Understanding & Search Notes
C.BEQZ uses CB format, compares restricted rs1' with implicit x0, and adds a sign-extended offset to PC when the condition is true.
rs1' can encode only x8-x15.
With the C extension, IALIGN=16, so a CB offset in 2-byte multiples satisfies instruction alignment.
Common Usage Scenarios
Address & Pointer
Understand this scenario with real code like «c.beqz x8, 32 # if x8==0 goto pc+32».
Pre-Use Checklist
Syntax Check
- Verify the 16-bit compressed encoding is only available on CPUs supporting the C extension.
- Confirm rd/rs1'/rs2' fields map to x8–x15.
Semantic Check
- Note the limited operand space of compressed instructions.
- Verify this compressed instruction has a corresponding 32-bit expansion.
Pitfalls / Common Confusions
Source register limited to x8-x15 (CB format)
The second comparison operand is implicit x0; this instruction has no destination register
Branch range only ±256 B (not ±4 KiB of 32-bit instructions)