C.BEQZ
RISC-V C.BEQZ Instruction Details
Instruction ManualC-typeBranch if rs1'==0 (±256B). CB format.
Instruction Syntax
c.beqz rs1', offset
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
CCompressed Instruction
Instruction Behavior
C.BEQZ (CB format, rs1' x8-x15 only) branches if rs1' equals zero. Sign-extended offset added to pc, ±256 B range. Expands to beq rs1',x0,offset.
Common Usage Scenarios
Address & Pointer
Understand this scenario with real code like «c.beqz x8, 32 # if x8==0 goto pc+32».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is C-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Source register limited to x8-x15 (CB format)
Unlike BEQ, implicit zero-register comparison only
Branch range only ±256 B (not ±4 KiB of 32-bit instructions)