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C.BNEZ

RISC-V C.BNEZ Instruction Details

Instruction ManualC-type

Branch if rs1'!=0 (±256B). CB format.

Instruction Syntax

c.bnez rs1', offset
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
CCompressed Instruction
Related Search Terms
C.BNEZ instructionRISC-V C.BNEZc.bnez syntaxc.bnez encodingc.bnez C-typec.bnez compressed instructionc.bnez branch

Instruction Behavior

C.BNEZ (CB format, rs1' x8-x15 only) branches if rs1' is nonzero. Sign-extended offset added to pc, ±256 B range. Expands to bne rs1',x0,offset.

C.BNEZ Decode & Execute Animation

This interactive model shows only architectural decode, operands, and state changes, not a pipeline, cache, or timing model.

c.bnez,
Execution context
Encoding fields
15..13
funct3
111
12
offset[8]
0
11..10
offset[4:3]
00
9..7
rs1'
000
6..5
offset[7:6]
00
4..3
offset[2:1]
00
2
offset[5]
1
1..0
op
01
Execution data path
Decode
CB: rs1' / permuted offset
Operands
x8 = 0x00000000, x0 = 0
Execute
comparison false, choose fall-through PC
State
PC <- 0x00001002

The zero-comparison condition is false.

Architectural result

Awaiting state update: the highlighted fields and calculation above show the current step; no architectural result has been committed yet.

Quick Understanding & Search Notes

C.BNEZ uses CB format; when restricted rs1' is nonzero, PC is updated by adding the sign-extended offset.

rs1' can encode only x8-x15.
When the condition is false, execution falls through to pc+2.
RISC-V Unprivileged ISA Manual: C extension control transfers

Common Usage Scenarios

Device & IO

Understand this scenario with real code like «c.bnez x8, 32 # if x8!=0 goto pc+32».

Loops & Iteration

Understand this scenario with real code like «c.bnez x8, 32 # if x8!=0 goto pc+32».

Pre-Use Checklist

Syntax Check
  • Verify the 16-bit compressed encoding is only available on CPUs supporting the C extension.
  • Confirm rd/rs1'/rs2' fields map to x8–x15.
Semantic Check
  • Note the limited operand space of compressed instructions.
  • Verify this compressed instruction has a corresponding 32-bit expansion.

Pitfalls / Common Confusions

Source register limited to x8-x15 (CB format)
The second comparison operand is implicit x0; this instruction has no destination register
Branch range only ±256 B (not ±4 KiB of 32-bit instructions)

FAQ

Does C.BNEZ compare two programmable registers?

No; its second operand is fixed as x0.