Does C.BNEZ compare two programmable registers?
No; its second operand is fixed as x0.
C.BNEZ
RISC-V C.BNEZ Instruction Details
Instruction ManualC-typeBranch if x[rs1'] is nonzero; otherwise PC+2. 16-bit CB format.
Instruction Syntax
c.bnez rs1', offset
Operand Breakdown
16-bit CB format; the 3-bit rs1' selects x8-x15 and the other comparison operand is fixed to x0.
offset is an even byte displacement from -256 through 254, sign-extended and added to the current instruction PC; zero is legal.
C.BNEZ branches when the register is nonzero; otherwise PC+2. There is no rd or link write.
CCompressed Instruction
Extension condition: RV32C / RV64C; this page describes C extension version 2.0.
Instruction Behavior
C.BNEZ uses the 16-bit CB format; its 3-bit rs1' selects x8-x15. If the register is nonzero, the target is the current instruction PC plus a sign-extended byte offset; otherwise execution continues at PC+2. The offset is even, from -256 through 254, including zero. It corresponds to bne rs1', x0, offset and writes no link register.
C.BNEZ Instruction Animation
Three learning stages illustrate architectural rules, without modeling processor pipelines or cycles.
c.bnez,
Execution context
RV32C / RV64C; C sets IALIGN=16, so PC is an even byte address. Address arithmetic wraps at XLEN. Subsequent target instruction-fetch exceptions are outside this model.
c.bnez → Condition false; PC ← 0x00001002; no link register write
16-bit encoding fields
0xE005
15..13
funct3
111
12
offset[8]
0
11..10
offset[4:3]
00
9..7
rs1'
000
6..5
offset[7:6]
00
4..3
offset[2:1]
00
2
offset[5]
1
1..0
op
01
Operands and calculation
Restore compressed operands
rs1'=000 → x8; rs2=x0=0; offset[8]=0; offset[4:3]=00; offset[7:6]=00; offset[2:1]=00; offset[5]=1; imm=000100000; sext(000100000) = 32 B; imm[0]=0; input offset is already in bytes, with no additional scaling.
Calculate
Not computed
Commit result
Pending commit
Architectural result
Architectural result not committed yet.
Quick Understanding & Search Notes
C.BNEZ uses CB format; when restricted rs1' is nonzero, PC is updated by adding the sign-extended offset.
rs1' can encode only x8-x15.
When the condition is false, execution falls through to pc+2.
Common Usage Scenarios
Conditional branch against zero
Understand this scenario with real code like «c.bnez x8, 32 # PC=0x1000: x8!=0 -> PC=0x1020; x8=0 -> PC=0x1002».
Pre-Use Checklist
Syntax Check
- Confirm RV32C / RV64C and the 16-bit encoding conditions.
- 16-bit CB format; the 3-bit rs1' selects x8-x15 and the other comparison operand is fixed to x0.
Semantic Check
- offset is an even byte displacement from -256 through 254, sign-extended and added to the current instruction PC; zero is legal.
- C.BNEZ branches when the register is nonzero; otherwise PC+2. There is no rd or link write.
Pitfalls / Common Confusions
Source register limited to x8-x15 (CB format)
The second comparison operand is implicit x0; this instruction has no destination register
The byte offset must be even, from -256 through 254; bit 0 is implicit zero and the target is relative to this instruction PC.