Does loading 0x80 produce a negative value?
No. It zero-extends the byte; a successful load of 0x80 gives 0x00000080 on RV32 or 0x0000000000000080 on RV64.
C.LBU
RISC-V C.LBU Instruction Details
Instruction ManualC-typeRV32/RV64 Zcb: load a byte at rs1'+offset 0–3, zero-extend to XLEN, and write rd'; both registers are x8–x15.
Instruction Syntax
c.lbu rd', uimm(rs1')
Operand Breakdown
RV32/RV64, Zcb 1.0.0 requiring Zca; 16-bit CLB format.
Three-bit rd' and rs1' both select x8–x15; uimm is an unscaled byte offset from 0 through 3.
Base plus zero-extended offset forms the address; a completed byte load is zero-extended to XLEN. Byte accesses are naturally aligned but still require EEI access conditions.
ZcbCompressed Instruction
Instruction Behavior
C.LBU (Zcb, CLB format) loads a byte from rs1' + zero-extended offset into rd', zero-extended to XLEN. rd' and rs1' limited to x8-x15. Expands to lbu rd',uimm(rs1'). Part of Zcb, depends on Zca.
C.LBU Compressed Encoding Lab
Explore the 16-bit encoding, operands, calculation, and architectural result.
c.lbu, ()
RV32/RV64, Zcb (requires Zca)
EA = 0x0000000000002000 + 1 = 0x0000000000002001 x9 <- 0x0000000000000080
16-bit encoding fields
15..10: funct6
100000
9..7: rs1'
010
6: uimm[0]
1
5: uimm[1]
0
4..2: rd'
001
1..0: op
00
rd' = 001 -> x9; rs1' = 010 -> x10
uimm[1:0] = 01; inst[6]=1, inst[5]=0 -> 1 (zero-extended, unscaled)
x10 + uimm = 0x0000000000002000 + 1 = 0x0000000000002001
mem[0x0000000000002001][7:0] = 0x80
EXTZ(byte) = 0x0000000000000080
Architectural state has not been committed.
Quick Understanding & Search Notes
RV32/RV64 Zcb: load a byte at rs1'+offset 0–3, zero-extend to XLEN, and write rd'; both registers are x8–x15.
CLB: funct6=100000, op=00; rs1'=[9:7], rd'=[4:2]; uimm[0]=bit6, uimm[1]=bit5, and all higher offset bits are zero.
Zcb 1.0.0 requires Zca; C alone does not include Zcb. Offsets are unscaled bytes from 0 through 3.
Byte accesses are always naturally aligned; the EEI determines accessible addresses, and a failed access does not produce a completed load.
Common Usage Scenarios
Arrays & Memory Access
RV32/RV64 Zcb, x10=0x2000 and mem[0x2001]=0x80, with a successful access: c.lbu x9, 1(x10) gives x9=0x80 with all higher bits zero.
Pre-Use Checklist
Syntax Check
- RV32/RV64, Zcb 1.0.0 requiring Zca; 16-bit CLB format.
- Three-bit rd' and rs1' both select x8–x15; uimm is an unscaled byte offset from 0 through 3.
Semantic Check
- Base plus zero-extended offset forms the address; a completed byte load is zero-extended to XLEN. Byte accesses are naturally aligned but still require EEI access conditions.
Pitfalls / Common Confusions
rd' and rs1' limited to x8-x15
Zero-extended offset, 2-bit unsigned offset, byte granularity
FAQ
Can the offset be negative, and does it need alignment?
The offset is an unsigned byte value from 0 through 3. Byte accesses are naturally aligned, while address validity and accessibility still depend on the EEI.