Is it always equivalent to a same-named 32-bit instruction?
Not always. Some C/Zc instructions compress common 32-bit operations, while others have dedicated stack-frame or table-jump semantics.
C.LBU
RISC-V C.LBU Instruction Details
Instruction ManualC-type16-bit encoding of lbu, zero-extended byte load
Instruction Syntax
c.lbu rd', uimm(rs1')
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
ZcbCompressed Instruction
Instruction Behavior
C.LBU (Zcb, CLB format) loads a byte from rs1' + zero-extended offset into rd', zero-extended to XLEN. rd' and rs1' limited to x8-x15. Expands to lbu rd',uimm(rs1'). Part of Zcb, depends on Zca.
C.LBU Decode & Execute Animation
Shows only official 16-bit decode, operands, computation, and architectural state; it does not simulate a pipeline, cache, or timing.
c.lbu, ()
Execution context
16-bit encoding fields
15..10
funct6
100000
9..7
rs1'
010
6
uimm[0]
1
5
uimm[1]
0
4..2
rd'
001
1..0
op
00
Execution data path
x10 + uimm = 0x0000000000002000 + 1 = 0x0000000000002001
mem[0x0000000000002001][7:0] = 0x80
EXTZ(byte) = 0x0000000000000080
Architectural state has not been committed.
Quick Understanding & Search Notes
C.LBU is the 16-bit encoding form for compressed unsigned byte load; its semantics and encodable register/immediate ranges must be read from the official C extension rules.
Compressed instructions often restrict register sets, immediate encodings, or destination registers; illegal combinations can be reserved.
Examples show assembly intent; actual encoding constraints follow the official C/Zc tables.
Common Usage Scenarios
Arrays & Memory Access
Understand this scenario with real code like «c.lbu x9, 1(x10) # zero-extended byte load».
Pre-Use Checklist
Syntax Check
- Verify the 16-bit compressed encoding is only available on CPUs supporting the C extension.
- Confirm rd/rs1'/rs2' fields map to x8–x15.
Semantic Check
- Note the limited operand space of compressed instructions.
- Verify this compressed instruction has a corresponding 32-bit expansion.
Pitfalls / Common Confusions
rd' and rs1' limited to x8-x15
Zero-extended offset, 2-bit unsigned offset, byte granularity
FAQ
Why do register restrictions matter?
Many 16-bit encodings can represent only a compressed register subset or fixed registers such as sp, ra, a0/a1.