Is it always equivalent to a same-named 32-bit instruction?
Not always. Some C/Zc instructions compress common 32-bit operations, while others have dedicated stack-frame or table-jump semantics.
C.LH
RISC-V C.LH Instruction Details
Instruction ManualC-type16-bit encoding of lh, sign-extended halfword load
Instruction Syntax
c.lh rd', uimm(rs1')
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
ZcbCompressed Instruction
Instruction Behavior
C.LH (Zcb, CLH format) loads a halfword from rs1' + zero-extended offset into rd', sign-extended to XLEN. rd' and rs1' limited to x8-x15. Expands to lh rd',uimm(rs1'). Offset is 1-bit unsigned ×2. Part of Zcb, depends on Zca.
C.LH Decode & Execute Animation
Shows only official 16-bit fields, address/immediate calculation, and architectural state; it does not simulate a pipeline, cache, endianness implementation, or timing.
c.lh, ()
Execution context
The EEI choice affects this result only when the effective address is not divisible by 2; a naturally aligned access must not raise an address-misaligned exception.
x[rs1'] + 2 -> 0x0000000000002002; sext(mem[0x0000000000002002][15:0] = 0x8001) = 0xFFFFFFFFFFFF8001
16-bit encoding fields
15..10
funct6
100001
9..7
rs1'
010
6
bit 6: signed
1
5
uimm[1]
1
4..2
rd'
001
1..0
op
00
Execution data path
Compressed fields: rd'=001 -> x9, rs1'=010 -> x10, uimm=2.
0x0000000000002000 + 2 = 0x0000000000002002
sext(mem[0x0000000000002002][15:0] = 0x8001) = 0xFFFFFFFFFFFF8001
Architectural state has not been committed.
Quick Understanding & Search Notes
C.LH is the 16-bit encoding form for compressed signed halfword load; its semantics and encodable register/immediate ranges must be read from the official C extension rules.
Compressed instructions often restrict register sets, immediate encodings, or destination registers; illegal combinations can be reserved.
Examples show assembly intent; actual encoding constraints follow the official C/Zc tables.
Common Usage Scenarios
Arrays & Memory Access
Understand this scenario with real code like «c.lh x9, 2(x10) # sign-extended halfword load».
Pre-Use Checklist
Syntax Check
- Verify the 16-bit compressed encoding is only available on CPUs supporting the C extension.
- Confirm rd/rs1'/rs2' fields map to x8–x15.
Semantic Check
- Note the limited operand space of compressed instructions.
- Verify this compressed instruction has a corresponding 32-bit expansion.
Pitfalls / Common Confusions
rd' and rs1' limited to x8-x15
Offset only 1-bit unsigned (0 or 2)
Sign-extended to XLEN
FAQ
Why do register restrictions matter?
Many 16-bit encodings can represent only a compressed register subset or fixed registers such as sp, ra, a0/a1.