Is it always equivalent to a same-named 32-bit instruction?
Not always. Some C/Zc instructions compress common 32-bit operations, while others have dedicated stack-frame or table-jump semantics.
C.LHU
RISC-V C.LHU Instruction Details
Instruction ManualC-type16-bit encoding of lhu, zero-extended halfword load
Instruction Syntax
c.lhu rd', uimm(rs1')
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
ZcbCompressed Instruction
Instruction Behavior
C.LHU (Zcb, CLH format) loads a halfword from rs1' + zero-extended offset into rd', zero-extended to XLEN. rd' and rs1' limited to x8-x15. Expands to lhu rd',uimm(rs1'). Part of Zcb, depends on Zca.
Quick Understanding & Search Notes
C.LHU is the 16-bit encoding form for compressed unsigned halfword load; its semantics and encodable register/immediate ranges must be read from the official C extension rules.
Compressed instructions often restrict register sets, immediate encodings, or destination registers; illegal combinations can be reserved.
Examples show assembly intent; actual encoding constraints follow the official C/Zc tables.
Common Usage Scenarios
Arrays & Memory Access
Understand this scenario with real code like «c.lhu x9, 2(x10) # zero-extended halfword load».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is C-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
rd' and rs1' limited to x8-x15
Offset only 1-bit unsigned (0 or 2 bytes)
FAQ
Why do register restrictions matter?
Many 16-bit encodings can represent only a compressed register subset or fixed registers such as sp, ra, a0/a1.