Which extensions does C.SEXT.H require?
It is a Zcb instruction, and the manual lists Zbb as an additional prerequisite; Zcb itself depends on Zca.
C.SEXT.H
RISC-V C.SEXT.H Instruction Details
Instruction ManualC-type16-bit sign-extend halfword (bit 15 replicated)
Instruction Syntax
c.sext.h rsd'
Operand Breakdown
RV32/RV64 Zcb requiring Zca and additionally Zbb; 16-bit CU format.
The sole three-bit rd'/rs1' field selects x8–x15 for both reading and writing; no immediate.
Only the low 16 bits contribute; sign-extend from bit 15 to XLEN and overwrite the same register.
x0 is outside the encodable compact-register set.
ZcbCompressed Instruction
Extension condition: RV32/RV64 Zcb, requiring Zca and additionally Zbb.
Instruction Behavior
C.SEXT.H uses the Zcb CU format. It sign-extends the least-significant halfword of rd'/rs1' to XLEN bits by copying halfword bit 15 into all upper bits. rd'/rs1' is limited to x8-x15, and Zbb is also required.
C.SEXT.H Decode & Execute Animation
Shows only official 16-bit fields, operands, conditions, and architectural state; it does not model a pipeline, cache, or timing.
c.sext.h
Execution context
RV32/RV64 Zcb + Zca + Zbb
x10=0x00008000 [15:0] → x10 <- 0xFFFF8000
16-bit encoding fields
15..10
funct6
100111
9..7
rd'/rs1'
010
6..5
funct2
11
4..2
C.SEXT.H
011
1..0
op
01
Execution data path
CU fields: rd'/rs1'=010 maps to x10; the same register is read and written.
EXTS(0x00008000[15:0] = 0x8000) = 0xFFFF8000
x10 <- 0xFFFF8000
Architectural state has not been committed.
Quick Understanding & Search Notes
C.SEXT.H reads the low 16 bits of rd'/rs1', sign-extends using bit 15, and writes the XLEN-bit result back to that register.
The three-bit CU rd'/rs1' field maps to x8-x15 and is both the source and destination register.
Only the low halfword contributes to the result: bit 15 is copied into all XLEN-16 upper bits; Zbb is an additional prerequisite.
Common Usage Scenarios
Signed halfword-value extension
RV32 Zcb+Zca+Zbb, x10=0x00008000: c.sext.h x10 writes x10=0xffff8000 (-32768). The RV64 result is 0xffffffffffff8000.
Pre-Use Checklist
Syntax Check
- RV32/RV64 Zcb requiring Zca and additionally Zbb; 16-bit CU format.
- The sole three-bit rd'/rs1' field selects x8–x15 for both reading and writing; no immediate.
Semantic Check
- Only the low 16 bits contribute; sign-extend from bit 15 to XLEN and overwrite the same register.
- x0 is outside the encodable compact-register set.
Pitfalls / Common Confusions
Requires Zbb
The sole rd'/rs1' operand is limited to x8-x15, and its former value is overwritten.
FAQ
Which bits determine the result?
Only the original low 16 bits of rd'/rs1' are used; bit 15 is copied into every higher bit and the result overwrites the same x8-x15 register.