Is it always equivalent to a same-named 32-bit instruction?
Not always. Some C/Zc instructions compress common 32-bit operations, while others have dedicated stack-frame or table-jump semantics.
C.SEXT.H
RISC-V C.SEXT.H Instruction Details
Instruction ManualC-type16-bit sign-extend halfword (bit 15 replicated)
Instruction Syntax
c.sext.h rsd'
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
ZcbCompressed Instruction
Instruction Behavior
C.SEXT.H (Zcb, CU format) sign-extends lower 16 bits of rsd' to XLEN (bit 15 replicated to upper bits). rsd' limited to x8-x15. Requires Zbb. Part of Zcb, depends on Zca and Zbb.
Quick Understanding & Search Notes
C.SEXT.H is the 16-bit encoding form for compressed sign-extend halfword; its semantics and encodable register/immediate ranges must be read from the official C extension rules.
Compressed instructions often restrict register sets, immediate encodings, or destination registers; illegal combinations can be reserved.
Examples show assembly intent; actual encoding constraints follow the official C/Zc tables.
Common Usage Scenarios
Arrays & Memory Access
Understand this scenario with real code like «c.sext.h x10 # x10 = EXTS(x10[15:0])».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is C-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Requires Zbb
Operand limited to x8-x15
FAQ
Why do register restrictions matter?
Many 16-bit encodings can represent only a compressed register subset or fixed registers such as sp, ra, a0/a1.