Which extensions does C.SEXT.H require?
It is a Zcb instruction, and the manual lists Zbb as an additional prerequisite; Zcb itself depends on Zca.
C.SEXT.H
RISC-V C.SEXT.H Instruction Details
Instruction ManualC-type16-bit sign-extend halfword (bit 15 replicated)
Instruction Syntax
c.sext.h rsd'
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
ZcbCompressed Instruction
Instruction Behavior
C.SEXT.H uses the Zcb CU format. It sign-extends the least-significant halfword of rd'/rs1' to XLEN bits by copying halfword bit 15 into all upper bits. rd'/rs1' is limited to x8-x15, and Zbb is also required.
C.SEXT.H Decode & Execute Animation
Shows only official 16-bit fields, operands, conditions, and architectural state; it does not model a pipeline, cache, or timing.
c.sext.h
Execution context
x10 <- 0xFFFF8000
16-bit encoding fields
15..10
funct6
100111
9..7
rd'/rs1'
010
6..5
funct2
11
4..2
C.SEXT.H
011
1..0
op
01
Execution data path
CU fields: rd'/rs1' maps to x10; the same register is read and written.
EXTS(X(x10)[15:0]) = 0xFFFF8000
x10 <- 0xFFFF8000
Architectural state has not been committed.
Quick Understanding & Search Notes
C.SEXT.H reads the low 16 bits of rd'/rs1', sign-extends using bit 15, and writes the XLEN-bit result back to that register.
The three-bit CU rd'/rs1' field maps to x8-x15 and is both the source and destination register.
Only the low halfword contributes to the result: bit 15 is copied into all XLEN-16 upper bits; Zbb is an additional prerequisite.
Common Usage Scenarios
Signed halfword-value extension
Understand this scenario with real code like «c.sext.h x10 # x10 = EXTS(x10[15:0])».
Pre-Use Checklist
Syntax Check
- Verify the 16-bit compressed encoding is only available on CPUs supporting the C extension.
- Confirm rd/rs1'/rs2' fields map to x8–x15.
Semantic Check
- Note the limited operand space of compressed instructions.
- Verify this compressed instruction has a corresponding 32-bit expansion.
Pitfalls / Common Confusions
Requires Zbb
The sole rd'/rs1' operand is limited to x8-x15, and its former value is overwritten.
FAQ
Which bits determine the result?
Only the original low 16 bits of rd'/rs1' are used; bit 15 is copied into every higher bit and the result overwrites the same x8-x15 register.