C.SLLI
RISC-V C.SLLI Instruction Details
Instruction ManualC-typeLogical left shift of rd. CI format.
Instruction Syntax
c.slli rd, uimm
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
CCompressed Instruction
Instruction Behavior
C.SLLI (CI format) shifts rd left logically by shamt, writes to rd. Expands to slli rd,rd,shamt[5:0]. In RV32C, shamt[5] must be 0. HINT when shamt=0 or rd=x0.
Common Usage Scenarios
Address & Pointer
Understand this scenario with real code like «c.slli x10, 2 # x10 <<= 2».
Multiplication & Division
Understand this scenario with real code like «c.slli x10, 2 # x10 <<= 2».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is C-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
HINT when shamt=0 or rd=x0