Is shamt=0 in C.SLLI an illegal instruction?
No. Within standard RV32C/RV64C encodings it is a HINT: registers and memory stay unchanged, while PC and applicable performance counters advance.
C.SLLI
RISC-V C.SLLI Instruction Details
Instruction ManualC-typeLogical left shift of rd. CI format.
Instruction Syntax
c.slli rd, uimm
Operand Breakdown
16-bit CI format; rd/rs1 is a full 5-bit field and updates the same register in place.
Ordinary shifts use 1–31 in RV32C or 1–63 in RV64C; shamt[5:0] is not byte-scaled.
Logical left shift fills with zeros and keeps the low XLEN bits; shamt=0 or rd=x0 is a HINT. RV32C shamt[5]=1 belongs to custom encoding space.
CCompressed Instruction
Related Search Terms
Instruction Behavior
C.SLLI uses CI format to logically shift the value in rd left by shamt and write it back to rd; it expands to slli rd, rd, shamt[5:0]. Code points with shamt=0 or rd=x0 are HINTs. In RV32C, shamt[5] must be zero; shamt[5]=1 code points are designated for custom extensions.
C.SLLI Decode & Execute Animation
c.slli,
RV32I + C extension; 16-bit encoding
Ordinary shifts retain the low XLEN bits. RV32C shamt[5]=1 belongs to custom space; HINTs do not commit an ordinary shift result.
0x00000003 << 2 = 0x0000000C (mod 2^32) → x10 <- 0x0000000C; PC+2
16-bit encoding fields
15..13
funct3
000
12
shamt[5]
0
11..7
rd/rs1
01010
6..2
shamt[4:0]
00010
1..0
op
10
Register mapping
rd/rs1=01010 -> x10
Immediate reconstruction
shamt[5]=0; shamt[4:0]=00010 -> 2
Calculation
Not calculated
Current architectural state
Not committed; registers, memory and PC retain their initial state.
Teaching stages show ISA-visible effects, not a CPU pipeline, cache, or timing model.
Quick Understanding & Search Notes
C.SLLI is a 16-bit CI logical left shift that updates rd in place; shamt=0 or rd=x0 is a HINT rather than ordinary C.SLLI execution.
In RV32C, shamt[5]=1 is designated for custom extensions and cannot be interpreted as standard C.SLLI.
Ordinary shifts use 1–31 in RV32C or 1–63 in RV64C; zeros fill the low bits and only the low XLEN bits remain.
Common Usage Scenarios
Shift Operations
Understand this scenario with real code like «c.slli x10, 2 # RV32C: x10=3 -> x10=12».
Pre-Use Checklist
Syntax Check
- Confirm RV32C / RV64C and the 16-bit encoding conditions.
- 16-bit CI format; rd/rs1 is a full 5-bit field and updates the same register in place.
Semantic Check
- Ordinary shifts use 1–31 in RV32C or 1–63 in RV64C; shamt[5:0] is not byte-scaled.
- Logical left shift fills with zeros and keeps the low XLEN bits; shamt=0 or rd=x0 is a HINT. RV32C shamt[5]=1 belongs to custom encoding space.
Pitfalls / Common Confusions
HINT when shamt=0 or rd=x0