Is it always equivalent to a same-named 32-bit instruction?
Not always. Some C/Zc instructions compress common 32-bit operations, while others have dedicated stack-frame or table-jump semantics.
C.SRLI
RISC-V C.SRLI Instruction Details
Instruction ManualC-typeLogical right shift of rd'. CB format.
Instruction Syntax
c.srli rd', uimm
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
CCompressed Instruction
Instruction Behavior
C.SRLI (CB format, rd' x8-x15 only) shifts rd' right logically by shamt. Expands to srli rd',rd',shamt. In RV32C, shamt[5] must be 0. HINT when shamt=0.
C.SRLI Decode & Execute Animation
Shows only official 16-bit fields, conditions, and architectural state; it does not model a pipeline, cache, or timing.
c.srli,
Execution context
x10 <- 0x10000002
16-bit encoding fields
15..13
funct3
100
12
shamt[5]
0
11..10
funct2
00
9..7
rd'/rs1'
010
6..2
shamt[4:0]
00011
1..0
op
01
Execution data path
CB fields restore rd'/rs1' to x10; shamt[5:0]=3.
0x80000010 >> 3 = 0x10000002
x10 <- 0x10000002
Architectural state has not been committed.
Quick Understanding & Search Notes
C.SRLI logically shifts rd' in x8-x15 right by shamt and writes the same register; shamt=0 is a HINT.
The CB rd'/rs1' three-bit field maps to x8-x15, and shamt is formed from bit 12 and bits 6:2.
In RV32C, shamt[5]=1 is designated for custom extensions; shamt=0 encodings are HINTs.
Common Usage Scenarios
Bit Operations & Masks
Understand this scenario with real code like «c.srli x8, 2 # x8 >>= 2 (logical)».
Vector Operations
Understand this scenario with real code like «c.srli x8, 2 # x8 >>= 2 (logical)».
Pre-Use Checklist
Syntax Check
- Verify the 16-bit compressed encoding is only available on CPUs supporting the C extension.
- Confirm rd/rs1'/rs2' fields map to x8–x15.
Semantic Check
- Note the limited operand space of compressed instructions.
- Verify this compressed instruction has a corresponding 32-bit expansion.
Pitfalls / Common Confusions
Destination register limited to x8-x15 (CB format)
RV32C: shamt[5]=0 required, shift range 0-31
Unlike C.SLLI, C.SRLI has restricted register access
FAQ
Why do register restrictions matter?
Many 16-bit encodings can represent only a compressed register subset or fixed registers such as sp, ra, a0/a1.