Is it always equivalent to a same-named 32-bit instruction?
Not always. Some C/Zc instructions compress common 32-bit operations, while others have dedicated stack-frame or table-jump semantics.
C.SRLI
RISC-V C.SRLI Instruction Details
Instruction ManualC-typeLogical right shift of rd'. CB format.
Instruction Syntax
c.srli rd', uimm
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
CCompressed Instruction
Instruction Behavior
C.SRLI (CB format, rd' x8-x15 only) shifts rd' right logically by shamt. Expands to srli rd',rd',shamt. In RV32C, shamt[5] must be 0. HINT when shamt=0.
Quick Understanding & Search Notes
C.SRLI is the 16-bit encoding form for compressed logical right shift immediate; its semantics and encodable register/immediate ranges must be read from the official C extension rules.
Compressed instructions often restrict register sets, immediate encodings, or destination registers; illegal combinations can be reserved.
Examples show assembly intent; actual encoding constraints follow the official C/Zc tables.
Common Usage Scenarios
Bit Operations & Masks
Understand this scenario with real code like «c.srli x8, 2 # x8 >>= 2 (logical)».
Vector Operations
Understand this scenario with real code like «c.srli x8, 2 # x8 >>= 2 (logical)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is C-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Destination register limited to x8-x15 (CB format)
RV32C: shamt[5]=0 required, shift range 0-31
Unlike C.SLLI, C.SRLI has restricted register access
FAQ
Why do register restrictions matter?
Many 16-bit encodings can represent only a compressed register subset or fixed registers such as sp, ra, a0/a1.