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C.SSPOPCHK

RISC-V C.SSPOPCHK Instruction Details

Instruction ManualC-type

C.SSPOPCHK reads the shadow return address at ssp and checks it against x1/x5.

Instruction Syntax

c.sspopchk x5
Operand Breakdown
Compressed instructions are 16 bits; registers are often limited to x8–x15.
Immediate fields are narrower. Refer to the full encoding for this compressed instruction.
ZicfissZcmopSecurity Mechanisms
Related Search Terms
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Instruction Behavior

C.SSPOPCHK x5 (Zicfiss, depends on Zcmop) expands to SSPOPCHK x5 for Zicfiss backward-edge CFI. It loads the shadow return address from ssp and compares it with x5, trapping on mismatch. Encoding reuses c.mop.5. Only effective when xSSE=1; otherwise executes as c.mop.5 (no-op).

Quick Understanding & Search Notes

C.SSPOPCHK belongs to the RISC-V CFI instruction set; behavior depends on whether Zicfilp/Zicfiss is enabled and on environment configuration.

Shadow-stack operations implicitly use ssp and XLEN width.
Do not mistake MOP compatibility for always-active security checks; inactive cases may degrade to no-op or zero-result behavior.
RISC-V Unprivileged ISA Manual: Control-Flow IntegrityRISC-V Unprivileged ISA Manual: Zimop/Zcmop May-Be-Operations

Common Usage Scenarios

Compressed & Code Size

Understand this scenario with real code like «c.sspopchk x5».

Register Operations

Understand this scenario with real code like «c.sspopchk x5».

Stack & Frame

Understand this scenario with real code like «c.sspopchk x5».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is C-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

Only x5 is provided in compressed form; SSPOPCHK itself supports x1 and x5.
Mismatch raises a software-check exception with shadow-stack fault code.
Zicfiss depends on Zicsr, Zimop, and Zaamo; compressed forms require Zcmop.
SSPOPCHK/C.SSPOPCHK increment ssp only after the load succeeds and comparison passes.

FAQ

What happens if the related CFI feature is inactive for C.SSPOPCHK?

Zicfiss instructions degrade according to the official Zimop/Zcmop-compatible behavior and do not perform shadow-stack checks or updates.

What official rule defines C.SSPOPCHK?

The Control-Flow Integrity chapter of the RISC-V Unprivileged ISA defines LPAD, SSPUSH, SSPOPCHK, SSRDP, and SSAMOSWAP.