Is czero.eqz a conditional branch?
No. Execution continues sequentially; it selects zero or rs1 based on whether rs2 is zero.
CZERO.EQZ
RISC-V CZERO.EQZ Instruction Details
Instruction ManualR-typeConditional zero: if rs2==0 then rd=0, else rd=rs1
Instruction Syntax
czero.eqz rd, rs1, rs2
Operand Breakdown
rd, rs1, rs2: integer registers x0–x31; x0 reads as zero and discards writes.
rs1 supplies the data value and rs2 supplies only the zero/nonzero condition; there is no immediate.
RV32/RV64 Zicond; write zero when rs2 is zero, otherwise copy rs1, without branching.
rd has syntactic dependencies on both sources; overlapping operands use values before writeback.
ZicondConditional Operations
Instruction Behavior
czero.eqz is a Zicond conditional-zero instruction. If rs2 is equal to zero, rd is written with zero; otherwise rd is written with rs1.
CZERO.EQZ Decode And Execute Animation
Starts with machine-code field decoding, then shows operand reads, instruction-specific execution, and ISA-visible state update.
rd
rs1
rs2
czero.eqz
,
,
Execution Context
This example uses fixed initial register values and PC=0x2000; instruction fetch succeeds, with no asynchronous interrupt or extra extension checks. Exception branches stop ordinary commit; post-trap PC and handler state are EEI-dependent.
t1(x6)
0x00000014
t2(x7)
0x00000007
31..25
24..20
19..15
14..12
11..7
6..0
0000111
funct7
00111
rs2
00110
rs1
101
funct3
00101
rd
0110011
opcode
Execution Data Path
instruction
0x0E7352B3
opcode
0110011 -> OP
funct3
101 -> CZERO.EQZ
funct7
0000111 -> Zicond conditional-zero selector
rd / value rs1 / condition rs2
t0(x5) / t1(x6)=0x00000014 / t2(x7)=0x00000007
conditional zero
Not computed
x5
t0(x5) = 0x00003001; pc = 0x00002000
Current Step
Concept Step: receive the 32-bit instruction encoding
The machine code is split by the current instruction format; the animation starts from encoding/decode.
encoding: 0x0E7352B3
syntax : czero.eqz t0(x5), t1(x6), t2(x7)
Result: Not computed
Current architectural state
t0(x5) = 0x00003001; pc = 0x00002000
This animation shows ISA-visible decode and state changes, not any specific CPU pipeline, cache, prediction, or timing implementation.
Quick Understanding & Search Notes
czero.eqz is a Zicond conditional-zero instruction. If rs2 is equal to zero, rd is written with zero; otherwise rd is written with rs1.
Zicond provides this R-type instruction on both RV32 and RV64; rs1 is the value and rs2 supplies the zero/nonzero condition.
It can be used to build branchless conditional-select sequences, but architecturally it only conditionally writes zero.
rd has syntactic dependencies on both rs1 and rs2, as defined by the official manual.
Common Usage Scenarios
Construct branchless conditional-select sequences
Understand this scenario with real code like «czero.eqz x10, x11, x12 ; x10 = (x12 == 0) ? 0 : x11».
Pre-Use Checklist
Syntax Check
- rd, rs1, rs2: integer registers x0–x31; x0 reads as zero and discards writes.
- rs1 supplies the data value and rs2 supplies only the zero/nonzero condition; there is no immediate.
Semantic Check
- RV32/RV64 Zicond; write zero when rs2 is zero, otherwise copy rs1, without branching.
- rd has syntactic dependencies on both sources; overlapping operands use values before writeback.
Pitfalls / Common Confusions
It selects zero or rs1, does not branch, and has no explicit data-memory access.
The condition tests whether rs2 is zero; it does not compare rs1 with rs2.
FAQ
Does czero.eqz compare two register magnitudes?
No. The condition only tests whether rs2 is zero.