RISC-V FADD.Q Instruction Details

Instruction ManualR-type

Performs quad-precision FP addition: rd = rs1+rs2. R-type, fmt=Q(11).

Instruction Syntax

fadd.q rd, rs1, rs2, rm

Operand Breakdown

rd: destination floating-point register receiving the formatted result.

rs1/rs2: source floating-point registers; arithmetic/rounding forms with rm use rm or dynamic frm for rounding mode.

QFloating-Point Arithmetic

Related Search Terms

fadd.q instruction quad-precision add fadd.q floating point fadd.q rounding NaN boxing

Instruction Behavior

fadd.q performs IEEE 754 addition on two quad-precision source operands, rounds according to rm, and writes the quad-precision result to f[rd].

Quick Understanding & Search Notes

fadd.q performs IEEE 754 addition on two quad-precision source operands, rounds according to rm, and writes the quad-precision result to f[rd].

The rm field selects a static rounding mode; rm=111 uses the dynamic frm rounding mode.

Results and exception flags follow RISC-V floating-point and IEEE 754 rules; do not treat NaN, infinity, or rounding boundaries like integer addition.

Source operands must satisfy the NaN-boxing rules for their floating-point format in FLEN registers.

RISC-V Unprivileged ISA Manual, Q quad-precision floating-point extension

Common Usage Scenarios

Floating Point Basic

Understand this scenario with real code like «fadd.q f0, f1, f2, rne # f0 = f1+f2».

Numerical Computing

Understand this scenario with real code like «fadd.q f0, f1, f2, rne # f0 = f1+f2».

Pre-Use Checklist

Syntax Check

Confirm the current instruction format is R-type.
Confirm the operand order matches the example.

Semantic Check

Ensure the destination register usage is compatible with the calling convention.
Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions