What does rm do for FADD.Q?
rm selects the floating-point rounding mode; rm=111 uses dynamic frm. If the result is exactly representable, rounding does not change the example value, but the encoded field still matters.
FADD.Q
RISC-V FADD.Q Instruction Details
Instruction ManualR-typeQuad-precision floating-point addition, OP-FP fmt=Q(11).
Instruction Syntax
fadd.q rd, rs1, rs2, rm
Operand Breakdown
rd, rs1, rs2: FP registers f0–f31 or their ABI names; f0 is writable.
rm: optional assembly operand, defaulting to dyn; rm=111 uses frm. Static 101/110 and dynamic 101/110/111 have reserved behavior.
QFloating-Point Arithmetic
Instruction Behavior
FADD.Q performs quad-precision floating-point addition on two FP source operands, rounds according to the rm field or dynamic frm, writes the result to FP register rd, and records fflags according to RISC-V floating-point rules.
FADD.Q Decode And Execute Animation
Shows the Q-extension quad-precision OP-FP flow: decode fields, read FP operands, perform FADD semantics, then write rd.
rd
rs1
rs2
rm
fadd.q
,
,
,
Leave rm empty to use the assembly default dyn encoding and fcsr.frm below.
Execution Context
FLEN=128 / fmt=Q (11)
rounding: RNE nearest-even
fflags: initial 0
31..27
26..25
24..20
19..15
14..12
11..7
6..0
00000
FADD
11
fmt=Q
01100
rs2
01011
rs1
000
rm
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0x06C58553
opcode
1010011 -> OP-FP
funct5/fmt
00000 + Q(11) -> FADD.Q
rm
000 -> RNE nearest-even
rd/rs
fa0(f10) / fa1(f11) / fa2(f12)
read
Source registers not read yet
FP op
Awaiting Execute
write
Not written yet; initial fflags=0
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; quad-precision OP-FP instructions use opcode 1010011.
encoding: 0x06C58553
syntax : fadd.q fa0(f10), fa1(f11), fa2(f12), rne
result : Not written yet; initial fflags=0
This animation accepts only finite whitelisted examples whose inputs and result are exactly checkable; this example needs no rounding and sets no FP exception flags. NaN, infinity, overflow, underflow, and inexact paths are covered in static text.
Quad-precision Calculation
rs1
fa1(f11) = 1.5
rs2
fa2(f12) = 1.5
result
Awaiting Execute
This animation accepts only finite whitelisted examples whose inputs and result are exactly checkable; this example needs no rounding and sets no FP exception flags. NaN, infinity, overflow, underflow, and inexact paths are covered in static text.
Assumes the extension is available, FS enabled, correctly NaN-boxed inputs, and initial fflags=0. Only nonzero finite exact whitelisted inputs and nonzero whitelisted results are accepted; zero and rounding/exception boundaries are outside this animation. One source register must have one initial value; rd may overlap a source, and f0 accepts writeback. Steps are teaching views.
This animation shows only Q-extension ISA-visible OP-FP encoding, example numeric results, and fflags relationship; it does not model FPU pipelines, latency, every IEEE 754 corner case, or microarchitecture.
Quick Understanding & Search Notes
FADD.Q is a Q-extension quad-precision OP-FP arithmetic instruction. It decodes funct5=00000 with fmt=Q(11), reads f[rs1] and f[rs2], performs addition, rounds by rm/frm, and writes f[rd].
fmt=Q(11) selects the quad-precision floating-point format; the opcode remains OP-FP 1010011.
The Q extension depends on D; FADD.Q sources and result are 128-bit quad-precision values.
The rm field selects a static rounding mode, while rm=111 uses dynamic frm; exact examples keep the same numeric value but the field is still encoded.
Applicable inexact, overflow, invalid-operation, and related cases are accrued in fflags; this is not integer arithmetic or condition-code update.
The Q extension provides the quad-precision format; this page animation shows only ISA-visible reads and writes of Q-format operands and results in FP registers, not narrower-format conversion.
Assembly rm is optional and defaults to dyn; explicit rounding mnemonics use lowercase. Behavior with static rm=101/110 or dynamic frm=101/110/111 is reserved.
FP exception flags accrue in fflags; setting a flag does not itself cause an FP exception trap. The animation starts with fflags=0 and accepts only nonzero finite examples with exact inputs and results.
Common Usage Scenarios
Floating-point arithmetic
Understand this scenario with real code like «fadd.q f0, f1, f2, rne # f0 = f1+f2».
Pre-Use Checklist
Syntax Check
- rd, rs1, rs2: FP registers f0–f31 or their ABI names; f0 is writable.
- rm: optional assembly operand, defaulting to dyn; rm=111 uses frm. Static 101/110 and dynamic 101/110/111 have reserved behavior.
Semantic Check
- Confirm 128-bit Q inputs use full FLEN=128.
- Inspect accrued fflags when needed; setting FP exception flags does not itself trap.
Pitfalls / Common Confusions
Results and exception flags follow RISC-V floating-point and IEEE 754 rules; do not treat NaN, infinity, or rounding boundaries like integer addition.
Q sets FLEN=128; FADD.Q uses full 128-bit Q values, not narrower values requiring upper bits filled with ones.
FAQ
Does FADD.Q write integer registers or condition codes?
FADD.Q writes FP register f[rd]. RISC-V floating-point exceptions are accrued in fflags, not reported through integer condition codes.