Quad-precision floating-point division: rd = rs1 / rs2.
32-bit OP-FP: opcode=1010011, funct5=00011, fmt=11; bits14:12 hold rm.
rd, rs1, rs2 are f0–f31 or ABI names; f0 is writable and rd may overlap a source. Optional rm defaults to dyn; rm=111 uses frm. Static 101/110 and dynamic frm=101–111 have reserved behavior.
RV32/RV64 Q (requires D and F), FLEN=128; enable required extensions and FP state. Sources narrower than FLEN require valid NaN-boxing, otherwise use canonical qNaN.
Divide quad-precision rs1 by rs2 and round with rm; the animation supports only nonzero finite exact whitelisted examples. fflags accrues NV/DZ/OF/UF/NX without a base FP exception trap on flag setting.
One source register must have one initial value. The animation starts with fflags=0; teaching steps are not hardware cycles.
FDIV.Q is a Q-extension quad-precision floating-point divide, and Q depends on D. It rounds the result according to the rm field or dynamic frm, then writes rd. Special values, NaNs, infinities, divide-by-zero cases, and exception flags follow the IEEE 754 rules adopted by the RISC-V floating-point extensions. rd, rs1, and rs2 are f0–f31; f0 is writable. Optional rm defaults to dyn in assembly.
Shows the Q-extension quad-precision OP-FP flow: decode fields, read FP operands, perform FDIV semantics, then write rd.
Leave rm empty to use the assembly default dyn encoding and fcsr.frm below.
The word is split as an R-type OP-FP instruction; quad-precision OP-FP instructions use opcode 1010011.
The default example 3.0 / 1.5 = 2.0 is exactly representable, so example fflags remains 0.
The default example 3.0 / 1.5 = 2.0 is exactly representable, so example fflags remains 0.
Assumes the extension is available, FS enabled, correctly NaN-boxed inputs, and initial fflags=0. Only nonzero finite exact whitelisted inputs and nonzero whitelisted results are accepted; zero and rounding/exception boundaries are outside this animation. One source register must have one initial value; rd may overlap a source, and f0 accepts writeback. Steps are teaching views.
This animation shows only Q-extension ISA-visible OP-FP encoding, example numeric results, and fflags relationship; it does not model FPU pipelines, latency, every IEEE 754 corner case, or microarchitecture.
FDIV.Q is a Q-extension quad-precision floating-point division; Q depends on D. It uses OP-FP encoding with funct5=00011 and fmt=Q(11), reads two quad-precision FP operands, rounds according to rm or dynamic frm, writes rd, and records applicable FP exceptions in fflags.
Understand this scenario with real code like «fdiv.q f0, f1, f2, rne # f0 = f1/f2».
Understand this scenario with real code like «fdiv.q f0, f1, f2, rne # f0 = f1/f2».
No. The animation shows ISA-visible encoding, field decode, operand reads, example calculation, and fflags relationship; it does not show FPU pipelines, latency, or full quad-precision implementation details.
The result is written to FP destination rd, and FP exception flags accrue in fflags. Divide-by-zero does not become an integer exception or an integer branch condition.