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FDIV.Q

RISC-V FDIV.Q Instruction Details

Instruction ManualR-type

Quad-precision floating-point division: rd = rs1 / rs2.

Instruction Syntax

fdiv.q rd, rs1, rs2, rm
Operand Breakdown
rd: destination floating-point register receiving the formatted result.
rs1/rs2: source floating-point registers; arithmetic/rounding forms with rm use rm or dynamic frm for rounding mode.
QFloating-Point Arithmetic
Related Search Terms
FDIV.Q instructionRISC-V FDIV.Qfdiv.q syntaxfdiv.q encodingfdiv.q roundingquad-precision FP divideRISC-V Q extension

Instruction Behavior

FDIV.Q performs quad-precision floating-point division for fdiv.q, rounds the result according to rm or the dynamic rounding mode, and writes rd. Special values, NaNs, infinities, divide-by-zero cases, and exception flags follow the IEEE 754 rules adopted by the RISC-V floating-point extensions.

FDIV.Q Decode And Execute Animation

Shows the Q-extension quad-precision OP-FP flow: decode fields, read FP operands, perform FDIV semantics, then write rd.

rd
rs1
rs2
rm
fdiv.q
,
,
,
Execution Context
FLEN=128 / fmt=Q (11)
rounding: RNE nearest-even
fflags: example fflags remains 0
31..27
26..25
24..20
19..15
14..12
11..7
6..0
00011
FDIV
11
fmt=Q
01100
rs2
01011
rs1
000
rm
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0x1EC58553
opcode
1010011 -> OP-FP
funct5/fmt
00011 + Q(11) -> FDIV.Q
rm
000 -> RNE nearest-even
rd/rs
fa0(f10) / fa1(f11) / fa2(f12)
read
3.0, 1.5
FP op
3.0 / 1.5 = 2.0
write
fa0(f10) = 2.0; example fflags remains 0
Current Step

Fetch: show the 32-bit OP-FP encoding

The word is split as an R-type OP-FP instruction; quad-precision OP-FP instructions use opcode 1010011.

encoding: 0x1EC58553
syntax : fdiv.q fa0(f10), fa1(f11), fa2(f12), rne
result : fa0(f10) = 2.0; example fflags remains 0

The default example 3.0 / 1.5 = 2.0 is exactly representable, so example fflags remains 0.

Quad-precision Calculation
rs1
fa1(f11) = 3.0
rs2
fa2(f12) = 1.5
result
3.0 / 1.5 = 2.0

The default example 3.0 / 1.5 = 2.0 is exactly representable, so example fflags remains 0.

This animation shows only Q-extension ISA-visible OP-FP encoding, example numeric results, and fflags relationship; it does not model FPU pipelines, latency, every IEEE 754 corner case, or microarchitecture.

Quick Understanding & Search Notes

FDIV.Q is Q-extension quad-precision floating-point division. It uses OP-FP encoding with funct5=00011 and fmt=Q(11), reads two quad-precision FP operands, rounds according to rm or dynamic frm, writes rd, and records applicable FP exceptions in fflags.

In OP-FP, opcode=1010011, funct5=00011 selects FDIV, and fmt=11 selects the Q quad-precision format.
The rm field selects a static rounding mode; rm=111 uses the dynamic frm rounding mode.
The animation computes only finite exactly checkable teaching examples; full quad-precision rounding, NaN, infinity, divide-by-zero, and overflow paths follow the official FP rules.
RISC-V Unprivileged ISA Manual: Q Extension

Common Usage Scenarios

Floating Point Basic

Understand this scenario with real code like «fdiv.q f0, f1, f2, rne # f0 = f1/f2».

Numerical Computing

Understand this scenario with real code like «fdiv.q f0, f1, f2, rne # f0 = f1/f2».

Pre-Use Checklist

Syntax Check
  • rd: destination floating-point register receiving the formatted result.
  • rs1/rs2: source floating-point registers; arithmetic/rounding forms with rm use rm or dynamic frm for rounding mode.
Semantic Check
  • Confirm the floating-point format suffix (.H/.S/.D/.Q) matches the data width.
  • Decide whether software must inspect fflags for NV, DZ, OF, UF, or NX.

Pitfalls / Common Confusions

Rounding comes from the rm field; rm=111 uses the dynamic frm rounding mode.
Floating-point exceptions are recorded in fflags, not as integer branch conditions or integer traps.
0/0, nonzero divided by zero, NaNs, and infinities follow IEEE 754/RISC-V floating-point result rules.

FAQ

Does the FDIV.Q animation model full quad-precision hardware?

No. The animation shows ISA-visible encoding, field decode, operand reads, example calculation, and fflags relationship; it does not show FPU pipelines, latency, or full quad-precision implementation details.

Where is the FDIV.Q divide-by-zero result recorded?

The result is written to FP destination rd, and FP exception flags accrue in fflags. Divide-by-zero does not become an integer exception or an integer branch condition.