RVOPcode
Home/Instructions/FSUB-Q
FSUB.Q

RISC-V FSUB.Q Instruction Details

Instruction ManualR-type

Quad-precision floating-point subtraction, OP-FP fmt=Q(11).

Instruction Syntax

fsub.q rd, rs1, rs2, rm
Operand Breakdown
rd: destination floating-point register receiving the formatted result.
rs1/rs2: source floating-point registers; arithmetic/rounding forms with rm use rm or dynamic frm for rounding mode.
QFloating-Point Arithmetic
Related Search Terms
FSUB.Q instructionRISC-V FSUB.Qfsub.q syntaxfsub.q encodingfsub.q roundingquad-precision FP subtractionRISC-V Q extension

Instruction Behavior

FSUB.Q performs quad-precision floating-point subtraction on two FP source operands, rounds according to the rm field or dynamic frm, writes the result to FP register rd, and records fflags according to RISC-V floating-point rules.

FSUB.Q Decode And Execute Animation

Shows the Q-extension quad-precision OP-FP flow: decode fields, read FP operands, perform FSUB semantics, then write rd.

rd
rs1
rs2
rm
fsub.q
,
,
,
Execution Context
FLEN=128 / fmt=Q (11)
rounding: RNE nearest-even
fflags: example fflags remains 0
31..27
26..25
24..20
19..15
14..12
11..7
6..0
00001
FSUB
11
fmt=Q
01100
rs2
01011
rs1
000
rm
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0x0EC58553
opcode
1010011 -> OP-FP
funct5/fmt
00001 + Q(11) -> FSUB.Q
rm
000 -> RNE nearest-even
rd/rs
fa0(f10) / fa1(f11) / fa2(f12)
read
3.5, 1.5
FP op
3.5 - 1.5 = 2.0
write
fa0(f10) = 2.0; example fflags remains 0
Current Step

Fetch: show the 32-bit OP-FP encoding

The word is split as an R-type OP-FP instruction; quad-precision OP-FP instructions use opcode 1010011.

encoding: 0x0EC58553
syntax : fsub.q fa0(f10), fa1(f11), fa2(f12), rne
result : fa0(f10) = 2.0; example fflags remains 0

This animation accepts only finite whitelisted examples whose inputs and result are exactly checkable; this example needs no rounding and sets no FP exception flags. NaN, infinity, overflow, underflow, and inexact paths are covered in static text.

Quad-precision Calculation
rs1
fa1(f11) = 3.5
rs2
fa2(f12) = 1.5
result
3.5 - 1.5 = 2.0

This animation accepts only finite whitelisted examples whose inputs and result are exactly checkable; this example needs no rounding and sets no FP exception flags. NaN, infinity, overflow, underflow, and inexact paths are covered in static text.

This animation shows only Q-extension ISA-visible OP-FP encoding, example numeric results, and fflags relationship; it does not model FPU pipelines, latency, every IEEE 754 corner case, or microarchitecture.

Quick Understanding & Search Notes

FSUB.Q is a Q-extension quad-precision OP-FP arithmetic instruction. It decodes funct5=00001 with fmt=Q(11), reads f[rs1] and f[rs2], performs subtraction, rounds by rm/frm, and writes f[rd].

fmt=Q(11) selects the quad-precision floating-point format; the opcode remains OP-FP 1010011.
The rm field selects a static rounding mode, while rm=111 uses dynamic frm; exact examples keep the same numeric value but the field is still encoded.
FSUB's applicable FP exception flags are NV, OF, and NX, accrued in fflags; this is not integer arithmetic or condition-code update.
The Q extension provides the quad-precision format; this page animation shows only ISA-visible reads and writes of Q-format operands and results in FP registers, not narrower-format conversion.
RISC-V Unprivileged ISA Manual, Q quad-precision floating-point extensionRISC-V Unprivileged ISA Manual, F extension rounding modes and fflags

Common Usage Scenarios

Floating-point arithmetic

Understand this scenario with real code like «fsub.q f0, f1, f2, rne # f0 = f1-f2».

Pre-Use Checklist

Syntax Check
  • rd: destination floating-point register receiving the formatted result.
  • rs1/rs2: source floating-point registers; arithmetic/rounding forms with rm use rm or dynamic frm for rounding mode.
Semantic Check
  • Confirm the floating-point format suffix (.H/.S/.D/.Q) matches the data width.
  • Decide whether software must inspect fflags for NV, DZ, OF, UF, or NX.

Pitfalls / Common Confusions

Rounding comes from the rm field; rm=111 uses the dynamic frm rounding mode.
Floating-point exceptions are recorded in fflags, not as integer branch conditions or integer traps.
FSUB's listed exception flags are NV, OF, and NX; they do not include UF.

FAQ

What does rm do for FSUB.Q?

rm selects the floating-point rounding mode; rm=111 uses dynamic frm. If the result is exactly representable, rounding does not change the example value, but the encoded field still matters.

Does FSUB.Q write integer registers or condition codes?

FSUB.Q writes FP register f[rd]. RISC-V floating-point exceptions are accrued in fflags, not reported through integer condition codes.