Convert unsigned 64-bit int to quad FP [RV64]. R-type, fmt=Q(11), rs2=source LU(11).
rd is FP f0–f31, including writable f0; rs1 is integer x0–x31, with x0 always reading 0. rs2 selects the source type; no immediate.
32-bit OP-FP: funct5=11010, fmt=11 (destination Q), rs2=00011, opcode=1010011.
RV64 only Q; Q depends on D, which depends on F. Enable required extensions and FP state. Finite conversion is exact and legal rm leaves the value unchanged.
Optional assembly rm defaults to dyn, using frm; software should select rne (000). Static rm=101/110 and dynamic frm=101–111 have reserved behavior even for exact conversions.
Interpret the 64 source bits as the selected signed/unsigned type, without FP NaN-boxing checks.
The Q result fills FLEN=128. Exceptions accrue in fflags; exact finite examples set no new flags and do not clear existing flags. Steps are teaching views.
fcvt.q.lu converts an unsigned 64-bit integer source to a quad-precision floating-point result. The conversion is exact; software should encode rm as RNE (000), while implementations still process legal and reserved rm encodings as usual.
Shows the Q-extension FCVT flow: decode OP-FP fields, fmt/rs2 conversion selection, the rm rounding field, read the integer source, then write the floating-point destination.
Leave rm empty for the assembly default dyn (111); this DYN example fixes frm=RNE. Use lowercase rne/rtz/rdn/rup/rmm/dyn only.
Assume required extensions and FP state are enabled, applicable source NaN-boxing is valid, and initial fflags=0. Results preview the current input; Writeback represents commit.
The word is split as an R-type OP-FP instruction; FCVT uses opcode 1010011.
The current 64-bit integer example is exactly representable as Q format, so example fflags remains 0.
The current 64-bit integer example is exactly representable as Q format, so example fflags remains 0.
This animation shows only Q-extension FCVT ISA-visible encoding, source/destination register direction, rounding field, and example fflags; it does not model FPU pipelines, exception handling, NaN payloads, or microarchitecture.
fcvt.q.lu converts an unsigned 64-bit integer source to a quad-precision floating-point result. The conversion is exact; software should encode rm as RNE (000), while implementations still process legal and reserved rm encodings as usual.
Understand this scenario with real code like «# x10 = 4097; initial fflags = 0; RV64 fcvt.q.lu f0, x10, rne # f0 = 4097 exactly; fflags = 0».
Every source integer is exactly representable in Q, so legal rm does not change the value. Decode rm normally: software should select rne; omission defaults to dyn, using frm, and reserved encodings retain reserved behavior.
It differs by source/destination format, integer signedness, RV64 restrictions, and whether rounding or invalid conversion can occur.