When does rm matter for fcvt.q.lu?
It does not matter for the numeric result. The source integer is exactly representable in the destination floating-point format, so rm does not cause rounding.
FCVT.Q.LU
RISC-V FCVT.Q.LU Instruction Details
Instruction ManualR-typeConvert unsigned 64-bit int to quad FP [RV64]. R-type, fmt=Q(11), rs2=source LU(11).
Instruction Syntax
fcvt.q.lu rd, rs1, rm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
QFloating-Point Convert
Instruction Behavior
fcvt.q.lu converts an unsigned 64-bit integer source to a quad-precision floating-point result. This conversion is exact, so the encoded rounding mode does not change the numeric result.
Quick Understanding & Search Notes
fcvt.q.lu converts an unsigned 64-bit integer source to a quad-precision floating-point result. This conversion is exact, so the encoded rounding mode does not change the numeric result.
The rs2/fmt encoding selects source and destination formats; the mnemonic suffixes carry the main semantic distinction.
This integer-to-floating-point conversion is exact; rm is encoded but does not change the numeric result.
L/LU 64-bit integer source forms are RV64-only.
The integer source operand comes from x[rs1], not a floating-point register, so there is no source NaN-boxing requirement.
The floating-point result is NaN-boxed in wider FLEN registers according to the destination format.
Common Usage Scenarios
Floating Point Basic
Understand this scenario with real code like «fcvt.q.lu f0, x10 # f0 = (quad)(ulong)x10 (RV64)».
Numerical Computing
Understand this scenario with real code like «fcvt.q.lu f0, x10 # f0 = (quad)(ulong)x10 (RV64)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
L/LU 64-bit integer source forms are RV64-only.
The integer source operand comes from x[rs1], not a floating-point register, so there is no source NaN-boxing requirement.
The floating-point result is NaN-boxed in wider FLEN registers according to the destination format.
FAQ
How does fcvt.q.lu differ from related FCVT instructions?
It differs by source/destination format, integer signedness, RV64 restrictions, and whether rounding or invalid conversion can occur.