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FCVT.Q.LU

RISC-V FCVT.Q.LU Instruction Details

Instruction ManualR-type

Convert unsigned 64-bit int to quad FP [RV64]. R-type, fmt=Q(11), rs2=source LU(11).

Instruction Syntax

fcvt.q.lu rd, rs1

Operand Breakdown

Destination rd: register receiving the operation result.

Source rs1: register holding the first operand.

Source rs2: register holding the second operand.

QFloating-Point Convert

Related Search Terms

fcvt.q.lu instruction unsigned 64-bit integer to quad-precision fcvt.q.lu conversion fcvt.q.lu exact conversion fcvt.q.lu floating point

Instruction Behavior

fcvt.q.lu converts an unsigned 64-bit integer source to a quad-precision floating-point result. The conversion is exact; software should encode rm as RNE (000), while implementations still process legal and reserved rm encodings as usual.

FCVT.Q.LU Decode And Execute Animation

Shows the Q-extension FCVT flow: decode OP-FP fields, fmt/rs2 conversion selection, an rm=000 encoding example, read the integer source, then write the floating-point destination.

rs1

fcvt.q.lu

Execution Context

fmt=Q (11)

rs2=LU

rounding: example rm=000; conversion never rounds

fflags: 0

RV64-only

a1(x11) source valueEnter a 64-bit integer or 0x hex; animation examples must fit the safe-integer range

31..27

26..25

24..20

19..15

14..12

11..7

6..0

11010

FCVT.Q

fmt=Q

00011

rs2=LU

01011

rs1

000

rm=000 example

01010

1010011

OP-FP

Execution Data Path

instruction

0xD6358553

opcode

1010011 -> OP-FP

funct5/fmt

11010 + 11 -> FCVT.Q.LU

rs2

00011 -> LU source

000 -> example encoding; conversion never rounds

rd/rs1

fa0(f10) / a1(x11)

read

a1(x11) = 0x00001001 (4097)

convert

uint64 0x00001001 (4097) -> Q 4097.0

write

fa0(f10) = 4097.0; 0

Current Step

Fetch: show the 32-bit OP-FP encoding

The word is split as an R-type OP-FP instruction; FCVT uses opcode 1010011.

encoding: 0xD6358553

syntax : fcvt.q.lu fa0(f10), a1(x11)

result : fa0(f10) = 4097.0; 0

The current 64-bit integer example is exactly representable as Q format, so example fflags remains 0.

FCVT Conversion View

LU source

0x00001001 (4097)

conversion

uint64 0x00001001 (4097) -> Q 4097.0

writeback

fa0(f10) = 4097.0

The current 64-bit integer example is exactly representable as Q format, so example fflags remains 0.

This animation shows only Q-extension FCVT ISA-visible encoding, source/destination register direction, rounding field, and example fflags; it does not model FPU pipelines, exception handling, NaN payloads, or microarchitecture.

Quick Understanding & Search Notes

The rs2/fmt encoding selects source and destination formats; the mnemonic suffixes carry the main semantic distinction.

This integer-to-floating-point conversion is exact; rm is encoded but does not change the numeric result.

L/LU 64-bit integer source forms are RV64-only.

The integer source operand comes from x[rs1], not a floating-point register, so there is no source NaN-boxing requirement.

The Q extension sets FLEN to 128 bits, so the quad-precision result is written directly to the destination FP register.

RISC-V Unprivileged ISA Manual, Q quad-precision floating-point extension

Common Usage Scenarios

Floating Point Basic

Understand this scenario with real code like «fcvt.q.lu f0, x10 # f0 = (quad)(ulong)x10 (RV64)».

Numerical Computing

Understand this scenario with real code like «fcvt.q.lu f0, x10 # f0 = (quad)(ulong)x10 (RV64)».

Pre-Use Checklist

Syntax Check

Verify rd, rs1, rs2 (and rs3) are valid GPRs.
Confirm funct3 and funct7 encoding is correct.

Semantic Check

Check if the result affects subsequent branches or address calculations.
Ensure the rd register is not overwritten by another instruction.

Pitfalls / Common Confusions