Is rd a floating-point register for FEQ.H?
No. rd is an integer register holding the Boolean result 0 or 1.
FEQ.H
RISC-V FEQ.H Instruction Details
Instruction ManualR-typeHalf-precision floating-point equality compare; writes x[rd]=1 when true, otherwise 0.
Instruction Syntax
feq.h rd, rs1, rs2
32-bit OP-FP: opcode=1010011, funct5=10100, fmt=10; funct3=010, no rm.
rd is integer x0–x31; rs1/rs2 are FP f0–f31 or ABI names. x0 discards the result while retaining NV side effects.
RV32/RV64 full Zfh (requires F, not Zfhmin); enable required extensions and FP state. Sources narrower than FLEN require valid NaN-boxing, otherwise use canonical qNaN.
Write 1 for equality, otherwise 0; any NaN writes 0. Only sNaN sets NV; qNaN does not clear old NV. fflags accrues exceptions.
One source register must have one initial value. The animation starts with fflags=0; teaching steps are not hardware cycles.
ZfhFloating-Point Compare
Instruction Behavior
FEQ.H belongs to Zfh, which depends on F, rather than Zfhmin's transfer/conversion-only subset. It compares the half-precision floating-point values in f[rs1] and f[rs2] and writes the Boolean result to integer register rd. The encoding uses the OP-FP opcode, funct5=10100, fmt=H(10), and funct3=010; it is a quiet comparison that sets NV only for signaling NaN, and any NaN operand makes the result 0.
FEQ.H Decode And Execute Animation
Shows the Zfh-extension half-precision OP-FP flow: decode fields, read FP operands, perform FEQ semantics, then write rd.
rd
rs1
rs2
feq.h
,
,
Execution Context
FLEN>=32 / fmt=H (10)
funct3: equality compare
fflags: initial 0
31..27
26..25
24..20
19..15
14..12
11..7
6..0
10100
FEQ
10
fmt=H
01100
rs2
01011
rs1
010
funct3=010
01010
rd
1010011
OP-FP
Execution Data Path
instruction
0xA4C5A553
opcode
1010011 -> OP-FP
funct5/fmt
10100 + H(10) -> FEQ.H
funct3
010 -> equality compare
rd/rs
a0(x10) / fa1(f11) / fa2(f12)
read
Source registers not read yet
FP op
Awaiting Execute
write
Not written yet; initial fflags=0
Current Step
Fetch: show the 32-bit OP-FP encoding
The word is split as an R-type OP-FP instruction; half-precision OP-FP instructions use opcode 1010011.
encoding: 0xA4C5A553
syntax : feq.h a0(x10), fa1(f11), fa2(f12)
result : Not written yet; initial fflags=0
The comparison result is written to integer register x[rd] and is only 0 or 1; compare instructions do not use rm.
Half-precision Calculation
rs1
fa1(f11) = 1.5
rs2
fa2(f12) = 1.5
result
Awaiting Execute
The comparison result is written to integer register x[rd] and is only 0 or 1; compare instructions do not use rm.
Assumes required extensions and FS enabled, valid NaN-boxing, and initial fflags=0. Finite inputs use the exact whitelist; signed zeros, infinities, qNaN, and sNaN are supported. Other inputs stop execution. One source register must have one initial value; rd=x0 discards only the integer write while NV still accrues. Steps are teaching views.
This animation shows only Zfh-extension ISA-visible OP-FP encoding, example numeric results, and fflags relationship; it does not model FPU pipelines, latency, every IEEE 754 corner case, or microarchitecture.
Quick Understanding & Search Notes
FEQ.H requires full Zfh, which depends on F, not Zfhmin; it writes the half-precision FP comparison result to integer register x[rd], and the result is only 0 or 1.
OP-FP opcode is 1010011; funct5=10100, fmt=10, and funct3=010 select FEQ.H.
FEQ.H requires full Zfh, which depends on F; Zfhmin contains only transfer and conversion instructions, not this compare.
It writes 1 when rs1 == rs2 is true, otherwise 0; any NaN operand writes 0.
FEQ is a quiet comparison: qNaN does not set NV, while sNaN sets NV.
The comparison produces no FP result and has no rm rounding field; rd is an integer register.
NV accrues: qNaN does not set NV or clear an existing NV flag. rd=x0 discards only the integer result; flag side effects remain.
When the source format is narrower than FLEN, an incorrectly NaN-boxed source is treated as canonical qNaN. The animation assumes valid NaN-boxing, required extensions and FP state enabled, and initial fflags=0.
Common Usage Scenarios
Comparison & Detection
Understand this scenario with real code like «feq.h x10, f0, f1 # f0=1.5, f1=1.5 -> x10=1; no new flags».
Floating-Point Conditions
Understand this scenario with real code like «feq.h x10, f0, f1 # f0=1.5, f1=1.5 -> x10=1; no new flags».
Pre-Use Checklist
Syntax Check
- rd: destination integer register receiving a 0 or 1 comparison result.
- rs1/rs2: source floating-point registers; compare instructions do not use an rm rounding mode.
Semantic Check
- Confirm the result is written to an integer register and is only 0 or 1.
- Confirm quiet/signaling comparison behavior for NaNs and NV matches the need.
Pitfalls / Common Confusions
Quiet comparisons set NV only for signaling NaNs; a quiet NaN only makes the result 0.
rd is an integer register and receives 0 or 1, not a floating-point value.
The comparison does not use the rm rounding mode.
FAQ
What happens on NaN operands for FEQ.H?
Any NaN operand makes the result 0; qNaN does not set NV, while sNaN sets NV.
Does FEQ.H use rm?
No. The funct3 field selects the comparison type, and the result is an integer Boolean.