RVOPcode
Home/Instructions/FEQ-Q
FEQ.Q

RISC-V FEQ.Q Instruction Details

Instruction ManualR-type

Quad-precision floating-point equality comparison; writes x[rd]=1 when true, otherwise 0.

Instruction Syntax

feq.q rd, rs1, rs2
Operand Breakdown
rd: destination integer register receiving a 0 or 1 comparison result.
rs1/rs2: source floating-point registers; compare instructions do not use an rm rounding mode.
QFloating-Point Compare
Related Search Terms
FEQ.Q instructionRISC-V FEQ.Qfeq.q syntaxfeq.q NaNfeq.q NV flagquad-precision floating compare

Instruction Behavior

FEQ.Q compares the quad-precision floating-point values in f[rs1] and f[rs2] and writes the Boolean result to integer register rd. It is a quiet comparison: quiet NaNs do not set NV, signaling NaNs set NV, and any NaN operand makes the result 0. The result is not a floating-point value and is not rounded by rm.

Quick Understanding & Search Notes

FEQ.Q writes the floating-point comparison result to integer register x[rd]. It has quiet-comparison semantics, useful when quiet NaNs should not raise NV.

It writes 1 when rs1 == rs2 is true, otherwise 0; any NaN operand writes 0.
The instruction does not produce a floating-point result and has no rm rounding field.
RISC-V Unprivileged ISA Manual: Q Extension

Common Usage Scenarios

Comparison & Detection

Understand this scenario with real code like «feq.q x10, f0, f1 # x10 = (f0==f1)».

Floating-Point Conditions

Understand this scenario with real code like «feq.q x10, f0, f1 # x10 = (f0==f1)».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is R-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

Quiet comparisons set NV only for signaling NaNs; a quiet NaN only makes the result 0.
rd is an integer register and receives 0 or 1, not a floating-point value.
The comparison does not use the rm rounding mode.

FAQ

Is rd a floating-point register for FEQ.Q?

No. rd is an integer register holding the Boolean result 0 or 1.

What happens on NaN operands?

Any NaN operand makes the result 0; only signaling NaNs set NV.