FEQ.Q

RISC-V FEQ.Q Instruction Details

Instruction ManualR-type

Quad-precision floating-point equality compare; writes x[rd]=1 when true, otherwise 0.

Instruction Syntax

feq.q rd, rs1, rs2

32-bit OP-FP: funct5[31:27]=10100, fmt[26:25]=11, rs2[24:20], rs1[19:15], funct3[14:12]=010, rd[11:7], opcode[6:0]=1010011; no rm.

rd is integer x0–x31 and rs1/rs2 are FP f0–f31; ABI names are accepted. x0 discards the Boolean result while NV still accrues. Integer and FP registers with the same index belong to separate register files.

Applies to RV32/RV64 Q (requires D and F), FLEN=128; enable required extensions and FP state. Sources narrower than FLEN require valid NaN-boxing, otherwise they are read as canonical qNaN.

Write 1 for equality, otherwise 0; any NaN writes 0. Only sNaN sets NV; qNaN neither sets NV nor clears old NV. fflags accrues exceptions; flag setting alone causes no base FP exception trap.

One source register must have one initial value. The animation starts with fflags=0 and accepts only listed exact finite values plus signed zeros, infinities, qNaN, and sNaN. Steps are teaching views.

QFloating-Point Compare

Related Search Terms

FEQ.Q instruction RISC-V FEQ.Q feq.q syntax feq.q encoding feq.q NaN feq.q NV flag quad-precision floating compare

Instruction Behavior

FEQ.Q compares the quad-precision floating-point values in f[rs1] and f[rs2] and writes the Boolean result to integer register rd. It requires Q (which depends on D, and D depends on F, with FLEN=128). The encoding uses the OP-FP opcode, funct5=10100, fmt=Q(11), and funct3=010; it is a quiet comparison that sets NV only for signaling NaN, and any NaN operand makes the result 0.

FEQ.Q Decode And Execute Animation

Shows the Q-extension quad-precision OP-FP flow: decode fields, read FP operands, perform FEQ semantics, then write rd.

rs1

rs2

feq.q

Execution Context

FLEN=128 / fmt=Q (11)

funct3: equality compare

fflags: initial 0

fa1(f11) valueExact whitelist: -3.5, -2, 0, 0.5, 1, 1.25, 1.5, 2, 2.25, 3, 3.5, 3.75, 5.25, 7, 7.5, 8; also signed zeros, qnan, snan, inf, -inffa2(f12) valueExact whitelist: -3.5, -2, 0, 0.5, 1, 1.25, 1.5, 2, 2.25, 3, 3.5, 3.75, 5.25, 7, 7.5, 8; also signed zeros, qnan, snan, inf, -inf

31..27

26..25

24..20

19..15

14..12

11..7

6..0

10100

FEQ

fmt=Q

01100

rs2

01011

rs1

010

funct3=010

01010

1010011

OP-FP

Execution Data Path

instruction

0xA6C5A553

opcode

1010011 -> OP-FP

funct5/fmt

10100 + Q(11) -> FEQ.Q

funct3

010 -> equality compare

rd/rs

a0(x10) / fa1(f11) / fa2(f12)

read

Source registers not read yet

FP op

Awaiting Execute

write

Not written yet; initial fflags=0

Current Step

Fetch: show the 32-bit OP-FP encoding

The word is split as an R-type OP-FP instruction; quad-precision OP-FP instructions use opcode 1010011.

encoding: 0xA6C5A553

syntax : feq.q a0(x10), fa1(f11), fa2(f12)

result : Not written yet; initial fflags=0

The comparison result is written to integer register x[rd] and is only 0 or 1; compare instructions do not use rm.

Quad-precision Calculation

rs1

fa1(f11) = 1.5

rs2

fa2(f12) = 1.5

result

Awaiting Execute

The comparison result is written to integer register x[rd] and is only 0 or 1; compare instructions do not use rm.

Assumes required extensions and FS enabled, valid NaN-boxing, and initial fflags=0. Finite inputs use the exact whitelist; signed zeros, infinities, qNaN, and sNaN are supported. Other inputs stop execution. One source register must have one initial value; rd=x0 discards only the integer write while NV still accrues. Steps are teaching views.

This animation shows only Q-extension ISA-visible OP-FP encoding, example numeric results, and fflags relationship; it does not model FPU pipelines, latency, every IEEE 754 corner case, or microarchitecture.

Quick Understanding & Search Notes

FEQ.Q writes the quad-precision FP comparison result to integer register x[rd]; the result is only 0 or 1.

OP-FP opcode is 1010011; funct5=10100, fmt=11, and funct3=010 select FEQ.Q.

It writes 1 when rs1 == rs2 is true, otherwise 0; any NaN operand writes 0.

FEQ is a quiet comparison: qNaN does not set or clear NV, while sNaN sets NV.

The comparison produces no FP result; bits[14:12] are funct3=010 selecting EQ, not an rm rounding mode; rd is an integer register.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Q v2.2, §23.4 The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — F v2.2, §21.8

Common Usage Scenarios

Comparison & Detection

Understand this scenario with real code like «feq.q x10, f0, f1 # x10 = (f0==f1)».

Floating-Point Conditions

Understand this scenario with real code like «feq.q x10, f0, f1 # x10 = (f0==f1)».

Pre-Use Checklist

Syntax Check

rd: destination integer register receiving a 0 or 1 comparison result.
rs1/rs2: source floating-point registers; compare instructions do not use an rm rounding mode.

Semantic Check

Confirm the result is written to an integer register and is only 0 or 1.
Confirm quiet/signaling comparison behavior for NaNs and NV matches the need.

Pitfalls / Common Confusions

FEQ sets NV only for sNaN; qNaN produces 0 without clearing an existing NV.

rd is an integer register and receives 0 or 1, not a floating-point value.

The comparison does not use the rm rounding mode.

fflags accrues exception flags; rd=x0 discards only the integer write, retaining NV side effects.

FAQ

Is rd a floating-point register for FEQ.Q?

No. rd is an integer register holding the Boolean result 0 or 1.

What happens on NaN operands for FEQ.Q?

Any NaN operand makes the result 0; qNaN does not set or clear NV, while sNaN sets NV.

Does FEQ.Q use rm?

No. The funct3 field selects the comparison type, and the result is an integer Boolean.