Is the FLQ offset encoded in multiples of 16 bytes?
No. offset is a signed 12-bit byte offset; natural alignment is an address property, not the encoding unit.
FLQ
RISC-V FLQ Instruction Details
Instruction ManualI-typeLoad a 128-bit quad-precision floating-point bit pattern from memory into an FP register.
Instruction Syntax
flq rd, offset(rs1)
Operand Breakdown
rd: destination floating-point register.
rs1: integer base-address register.
offset: signed 12-bit byte offset added to rs1 to form the effective address.
QFloating-Point Load
Instruction Behavior
FLQ uses the I-type LOAD-FP encoding to load a 128-bit quad-precision floating-point bit pattern from the effective address x[rs1] plus a signed 12-bit byte offset into floating-point register f[rd]. The transfer performs no FP rounding, format conversion, or NaN payload canonicalization. The official Q extension guarantees FLQ access atomicity only when the effective address is naturally aligned and XLEN=128; misaligned access is constrained by the execution environment.
FLQ Decode And Execute Animation
Shows the Q-extension FP load flow: decode the I-type encoding, form the address from an integer base plus a 12-bit offset, and transfer a 128-bit FP bit pattern.
rd
offset
rs1
flq
,
,
Execution Context
fmt=Q / width=128
base register is an integer x register
fflags unchanged
31..20
19..15
14..12
11..7
6..0
000000100000
imm[11:0]
01010
rs1
100
FLQ
01010
rd
0000111
LOAD-FP
Execution Data Path
instruction
0x02054507
opcode
0000111 -> LOAD-FP
funct3
100 -> 128-bit load
offset
000000100000 -> 32
rd/rs1
fa0(f10) / a0(x10)
read
a0(x10) = 0x0000000000001000
address
0x0000000000001000 + (32) = 0x0000000000001020
write
fa0(f10) = 0x3FFF8000000000000000000000000000
Current Step
Fetch: show the 32-bit I-type encoding
The word is split as a I-type instruction; FP memory access is not an OP-FP arithmetic encoding.
encoding: 0x02054507
syntax : flq fa0(f10), 32(a0(x10))
result : fa0(f10) = 0x3FFF8000000000000000000000000000
Address And Bit-Pattern Transfer
base
0x0000000000001000
offset
32
address
0x0000000000001020
loaded bits
0x3FFF8000000000000000000000000000
FLQ transfers a 128-bit quad-precision bit pattern; the official Q extension guarantees access atomicity only for naturally aligned effective addresses when XLEN=128.
This animation shows only Q-extension FP load/store ISA-visible address calculation and bit-pattern transfer; it does not model caches, buses, trap handlers, FPU pipelines, or microarchitectural timing.
Quick Understanding & Search Notes
FLQ is the Q-extension quad-precision floating-point load. It forms the address from integer register rs1 plus a signed 12-bit byte offset, then loads a 128-bit quad-precision bit pattern into FP register rd; this is not FP arithmetic and does not use rm rounding.
I-type LOAD-FP: imm[11:0], rs1, funct3=100, rd, opcode=0000111.
Effective address = x[rs1] + sign_extend(offset), with the offset measured in bytes.
FLQ transfers a 128-bit quad-precision bit pattern; naturally aligned access is atomic when XLEN=128.
Common Usage Scenarios
Floating-Point Memory
Understand this scenario with real code like «flq f0, 0(x10) # load quad from [x10+0]».
Data Load/Store
Understand this scenario with real code like «flq f0, 0(x10) # load quad from [x10+0]».
Pre-Use Checklist
Syntax Check
- rd: destination floating-point register.
- rs1: integer base-address register.
- offset: signed 12-bit byte offset added to rs1 to form the effective address.
Semantic Check
- Confirm offset is a byte offset, not an element index.
- Check natural alignment and the execution environment's misaligned-access rules.
Pitfalls / Common Confusions
rs1 is an integer base register, not an FP register; rd is the quad-precision FP destination register.
offset is a signed 12-bit byte offset in -2048..2047, not an encoded multiple of 16 bytes.
FLQ transfers a 128-bit bit pattern and performs no FP rounding, format conversion, or NaN payload canonicalization.
The access atomicity guarantee requires natural alignment and XLEN=128; do not treat misaligned FLQ as a portable synchronization primitive.
FAQ
Does FLQ change a NaN payload?
No. FLQ is a bit-pattern load, and the transfer does not canonicalize NaN payloads.