Does FSQ take the address from an FP register?
No. The address base comes from integer register rs1; FP register rs2 only supplies the data bit pattern to store.
FSQ
RISC-V FSQ Instruction Details
Instruction ManualS-typeStore a 128-bit quad-precision bit pattern from an FP register to memory.
Instruction Syntax
fsq rs2, offset(rs1)
Operand Breakdown
rs2 selects FP f0–f31 and rs1 selects integer x0–x31; x0 supplies zero and f0 is an ordinary FP source. offset is a signed byte displacement in -2048..2047.
32-bit S-type STORE-FP: imm[11:5] | rs2 | rs1 | funct3=100 | imm[4:0] | opcode=0100111.
Requires Q 2.2 (dependent on D), FLEN=128 and enabled FP state. Add the sign-extended offset to x[rs1], wrapping to XLEN. A successful store preserves all 128 bits without rounding, fflags changes, or source/base register changes.
Atomicity is guaranteed with 16-byte natural alignment and XLEN=128; FSQ is also available on RV32/RV64. The EEI determines misaligned handling. An exception does not guarantee that all memory remains unchanged.
QFloating-Point Store
Instruction Behavior
FSQ uses the S-type STORE-FP encoding to store the 128-bit quad-precision floating-point bit pattern from floating-point register f[rs2] to the effective address x[rs1] plus a signed 12-bit byte offset. The store writes the format-width bits and performs no FP rounding, format conversion, or NaN payload canonicalization. The official Q extension guarantees FSQ access atomicity only when the effective address is naturally aligned and XLEN=128; misaligned access is constrained by the execution environment.
FSQ Decode And Execute Animation
Shows the Q-extension FP store flow: decode the S-type encoding, form the address from an integer base plus a 12-bit offset, and transfer a 128-bit FP bit pattern.
rs2
offset
rs1
fsq
,
,
Execution Context
fmt=Q / width=128
base register is an integer x register
fflags unchanged
31..25
24..20
19..15
14..12
11..7
6..0
0000001
imm[11:5]
01011
rs2
01010
rs1
100
FSQ
00000
imm[4:0]
0100111
STORE-FP
Execution Data Path
instruction
0x02B54027
opcode
0100111 -> STORE-FP
funct3
100 -> 128-bit store
offset
000000100000 -> 32
rs2/rs1
fa1(f11) / a0(x10)
read
a0(x10) = 0x0000000000001000, fa1(f11) = 0x3FFF8000000000000000000000000000
address
Awaiting Address
memory
Not stored yet; memory not updated
Current Step
Fetch: show the 32-bit S-type encoding
The word is split as a S-type instruction; FP memory access is not an OP-FP arithmetic encoding.
encoding: 0x02B54027
syntax : fsq fa1(f11), 32(a0(x10))
result : Not stored yet; memory not updated
Address And Bit-Pattern Transfer
base
0x0000000000001000
offset
32
address
Awaiting Address
alignment
16-byte aligned
atomicity
not guaranteed
stored bits
Not stored yet; memory not updated
FSQ transfers a 128-bit quad-precision bit pattern. The official atomic-execution guarantee applies only when the effective address is naturally aligned and XLEN=128. This example is naturally aligned and cannot raise address-misaligned.
Assumes the extension and FS are enabled and the address is accessible. Shows the selected EEI branch without modeling protection or translation. The source input supplies the low bits; stores ignore higher bits without checking NaN-boxing. Steps are teaching views.
This animation shows only Q-extension FP load/store ISA-visible address calculation and bit-pattern transfer; it does not model caches, buses, trap handlers, FPU pipelines, or microarchitectural timing.
Quick Understanding & Search Notes
FSQ is the Q-extension quad-precision floating-point store. It computes the address from an integer base and a 12-bit byte offset, then writes the 128-bit quad-precision bit pattern from f[rs2] to memory; it is not FP arithmetic and has no rm rounding step.
S-type STORE-FP: imm[11:5], rs2, rs1, funct3=100, imm[4:0], opcode=0100111.
Effective address = x[rs1] + sign_extend(offset), with the offset measured in bytes.
FSQ stores the 128-bit quad-precision encoding from the source FP register without canonicalizing NaN payloads.
Requires Q 2.2 (dependent on D), FLEN=128, and enabled FP state. FSQ is also available on RV32/RV64; XLEN=128 is a condition of the atomicity guarantee. Natural alignment is 16 bytes; the EEI determines misaligned handling.
Common Usage Scenarios
Floating-Point Memory
Understand this scenario with real code like «fsq f0, 0(x10) # store quad to [x10+0]».
Data Load/Store
Understand this scenario with real code like «fsq f0, 0(x10) # store quad to [x10+0]».
Pre-Use Checklist
Syntax Check
- rs2 selects FP f0–f31 and rs1 selects integer x0–x31; x0 supplies zero and f0 is an ordinary FP source. offset is a signed byte displacement in -2048..2047.
- 32-bit S-type STORE-FP: imm[11:5] | rs2 | rs1 | funct3=100 | imm[4:0] | opcode=0100111.
Semantic Check
- Requires Q 2.2 (dependent on D), FLEN=128 and enabled FP state. Add the sign-extended offset to x[rs1], wrapping to XLEN. A successful store preserves all 128 bits without rounding, fflags changes, or source/base register changes.
- Atomicity is guaranteed with 16-byte natural alignment and XLEN=128; FSQ is also available on RV32/RV64. The EEI determines misaligned handling. An exception does not guarantee that all memory remains unchanged.
Pitfalls / Common Confusions
rs1 is an integer base register; rs2 is the quad-precision FP source register.
offset is a signed 12-bit byte offset in -2048..2047.
FSQ stores a 128-bit quad-precision bit pattern and performs no FP rounding or format conversion.
The access atomicity guarantee requires natural alignment and XLEN=128; misaligned handling is constrained by the execution environment.
FAQ
Does FSQ change fflags?
No. FSQ is a bit-pattern store and performs no FP arithmetic or rounding, so it does not set floating-point exception flags by ISA-visible semantics.