Can it execute in U-mode?
With H implemented: M/HS or V=0 U-mode with HU=1 may execute. V=0 U-mode with HU=0 raises illegal-instruction; V=1 raises virtual-instruction.
HLV.BU
RISC-V HLV.BU Instruction Details
Instruction ManualSYSTEM (R-type encoding)Hypervisor virtual-machine load of a zero-extended byte using VS/VU effective privilege and two-stage translation.
Instruction Syntax
hlv.bu rd, (rs1)
Operand Breakdown
Destination rd: receives the zero-extended 8-bit loaded value; when rd=x0 the writeback value is discarded, but the explicit access still executes.
Address register rs1: directly supplies the explicit-access address; HLV.BU assembly has no offset immediate field.
The SYSTEM encoding fixes funct7=0110000, rs2=00001, funct3=100, and opcode=1110011; do not decode it as an ordinary I-type load.
HSystem & Privilege
Instruction Behavior
HLV.BU is the H-extension virtual-machine load corresponding to LBU. It reads an 8-bit value at the address in rs1 and zero-extends it to XLEN; the instruction has no immediate offset. It is valid only in M-mode, HS-mode, or U-mode with hstatus.HU=1. The explicit access uses VU effective privilege when hstatus.SPVP=0 and VS effective privilege when SPVP=1, with VS-stage and G-stage translation.
HLV.BU Decode And Execute Animation
Shows HLV.BU SYSTEM decoding, privilege checks, two-stage translation, and zero-extended writeback without modeling page walks or TLB implementation.
rd
rs1
hlv.bu,()
Assumes H is implemented, relevant privilege modes use the same XLEN, and pointer masking is disabled. Input is an assembled memory value; the selector supplies the access outcome without validating page tables. rs1=x0 fixes address zero. Steps are teaching stages, not processor cycles.
31..25
24..20
19..15
14..12
11..7
6..0
0110000
funct7
00001
rs2[0]=U
01011
rs1/address
100
PRIVM
01010
rd
1110011
SYSTEM
Architectural Data Path
instruction
0x6015C573
decode
funct7=0110000, rs2=00001, funct3=100, rd=01010 -> HLV.BU
address
a1(x11) -> 0x0000000040001000 (no immediate offset)
privilege
HS: execution permitted
translation
VU effective privilege -> VS-stage -> G-stage; HS SUM ignored; MPRV is not used
load
8-bit 0x80 -> zero-extend -> 0x0000000000000080
state
Architectural state is not committed; the final rd state is shown only at writeback.
Architectural state is not committed; the final rd state is shown only at writeback.
This animation shows only official architectural conditions and outcomes; page walks, TLBs, caches, and platform exception handling are not modeled.
Quick Understanding & Search Notes
HLV.BU reads 8 bits at rs1, zero-extends to XLEN into rd.
SPVP=0/1 selects VU/VS. HS-level SUM is ignored; MPRV has no effect.
HS-level MXR applies to both stages; vsstatus.MXR only to VS-stage. Either stage may be Bare.
rd=x0 discards only the value; exceptions and side effects remain. rs1=x0 supplies address zero.
Common Usage Scenarios
Virtual-machine memory load
Understand this scenario with real code like «# RV64; H 扩展 / H extension; HS-mode, SPVP=0; pointer masking disabled # x11=0x40001000; VS/G-stage access succeeds # 8-bit memory value = 0x80 hlv.bu x10, (x11) # x10 = 0x0000000000000080».
VS/VU effective privilege
Understand this scenario with real code like «# RV64; H 扩展 / H extension; HS-mode, SPVP=0; pointer masking disabled # x11=0x40001000; VS/G-stage access succeeds # 8-bit memory value = 0x80 hlv.bu x10, (x11) # x10 = 0x0000000000000080».
Two-stage address translation
Understand this scenario with real code like «# RV64; H 扩展 / H extension; HS-mode, SPVP=0; pointer masking disabled # x11=0x40001000; VS/G-stage access succeeds # 8-bit memory value = 0x80 hlv.bu x10, (x11) # x10 = 0x0000000000000080».
Pre-Use Checklist
Syntax Check
- Confirm the assembly syntax is hlv.bu rd, (rs1): rs1 supplies the address directly and there is no offset immediate.
- Confirm the SYSTEM encoding fixes rs2=00001, funct7=0110000, funct3=100, and opcode=1110011.
Semantic Check
- Confirm execution is in M/HS, or in U-mode with hstatus.HU=1; V=1 raises a virtual-instruction exception.
- Confirm the 8-bit load uses zero extension, and preserve handling for VS-stage/G-stage access faults, page faults, and guest-page faults.
Pitfalls / Common Confusions
Executing HLV/HLVX/HSV when virtualization mode V=1 raises a virtual-instruction exception.
U-mode execution is legal only when hstatus.HU=1; otherwise it raises illegal-instruction.
Access faults, guest-page faults, and page faults are still possible under the VS/G-stage translations.
FAQ
What happens with rs1=x0 or rd=rs1?
rs1=x0 supplies zero. With rd=rs1, read the address before writeback. rd=x0 retains exceptions and side effects.