Is it a normal user-mode instruction?
No. It is valid only in M-mode, HS-mode, or U-mode with hstatus.HU=1; an attempt while V=1 raises a virtual-instruction exception.
HLV.B
RISC-V HLV.B Instruction Details
Instruction ManualSYSTEM R-typeHypervisor virtual-machine load: use rs1 as the address, translate with VS/VU effective privilege, then sign-extend the loaded byte to XLEN.
Instruction Syntax
hlv.b rd, (rs1)
Operand Breakdown
This is a SYSTEM R-type-format instruction. Confirm operand positions based on the assembly syntax.
HSystem & Privilege
Instruction Behavior
HLV.B is the H-extension virtual-machine load corresponding to LB. It has no immediate offset: rs1 supplies the address of the explicit access. The loaded 8-bit value is sign-extended to XLEN and written to rd (with rd=x0, the value is discarded but the load can still raise exceptions or cause other side effects). It is valid only in M-mode, HS-mode, or U-mode with hstatus.HU=1. The explicit access uses VU effective privilege when hstatus.SPVP=0 and VS effective privilege when SPVP=1, with VS-stage and G-stage translation.
HLV.B Decode And Execute Animation
Shows HLV.B SYSTEM decoding, privilege checks, two-stage translation, and sign-extended writeback without modeling page walks or TLB implementation.
rd
rs1
hlv.b,()
31..25
24..20
19..15
14..12
11..7
6..0
0110000
funct7
00000
rs2=x0
01011
rs1/address
100
PRIVM
01010
rd
1110011
SYSTEM
Architectural Data Path
instruction
0x6005C573
decode
funct7=0110000, rs2=00000, funct3=100, rd=01010 -> HLV.B
address
a1(x11) -> 0x0000000040001000 (no immediate offset)
privilege
HS: execution permitted
translation
VU effective privilege -> VS-stage -> G-stage; HS SUM ignored; MPRV is not used
load
8-bit 0x80 -> sign-extend (-128) -> 0xFFFFFFFFFFFFFF80
state
Architectural state is not committed; the final rd state is shown only at writeback.
Architectural state is not committed; the final rd state is shown only at writeback.
This animation shows only official architectural conditions and outcomes; page walks, TLBs, caches, and platform exception handling are not modeled.
Quick Understanding & Search Notes
HLV.B is the H-extension virtual-machine signed byte load: rs1 supplies the address, and the memory access uses VS/VU effective privilege through VS-stage and G-stage translation.
funct7=0110000, rs2=x0, funct3=100, rd/rs1, and opcode=1110011 form the HLV.B SYSTEM R-type encoding.
HLV.B corresponds to LB: it reads 8 bits at rs1 and sign-extends to XLEN; it has no immediate offset.
Execution permission, virtual-instruction exceptions, and two-stage translation conditions follow the H-extension privileged rules.
Common Usage Scenarios
Hypervisor device emulation
Understand this scenario with real code like «hlv.b a0, (a1)».
Guest memory access
Understand this scenario with real code like «hlv.b a0, (a1)».
Virtual-machine load
Understand this scenario with real code like «hlv.b a0, (a1)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is SYSTEM R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Executing HLV/HLVX/HSV when virtualization mode V=1 raises a virtual-instruction exception.
U-mode execution is legal only when hstatus.HU=1; otherwise it raises illegal-instruction.
Access faults, guest-page faults, and page faults are still possible under the VS/G-stage translations; rd is not written when the access traps.
The encoding fixes funct7=0110000, rs2=x0, funct3=100, and opcode=1110011; this is not ordinary I-type LB with a 12-bit offset.
FAQ
Does HLV.B have an immediate address offset?
No. HLV.B takes its address from rs1; its SYSTEM R-type encoding fixes rs2=x0 instead of using the ordinary LB 12-bit I-type offset field.