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HLV.B

RISC-V HLV.B Instruction Details

Instruction ManualI-type

Hypervisor virtual-machine load of a signed byte using VS/VU effective privilege and two-stage translation.

Instruction Syntax

hlv.b rd, (rs1)
Operand Breakdown
Destination rd: general-purpose register receiving the result.
Source rs1: register holding the first operand.
Immediate imm: 12-bit signed value, sign-extended before operation with rs1.
HSystem & Privilege
Related Search Terms
HLV.B instructionRISC-V HLV.Bhlv.b syntaxhlv.b encodinghlv.b Hhlv.b virtual loadhlv.b VS-stage

Instruction Behavior

HLV.B is the H-extension virtual-machine load corresponding to LB. It may execute in M-mode or HS-mode, or in U-mode when hstatus.HU=1. The explicit memory access uses effective privilege VU when hstatus.SPVP=0 and VS when hstatus.SPVP=1, with two-stage address translation.

Quick Understanding & Search Notes

HLV.B is the H-extension virtual-machine signed byte load, loading through VS-stage and G-stage translation using the memory access's VS/VU effective privilege.

Execution permission, trap type, and state restoration depend on privilege level, relevant CSR bits, and extension presence.
H-extension memory/fence instructions involve VS-stage and G-stage two-stage translation.
RISC-V Privileged Architecture Manual, Hypervisor Extension

Common Usage Scenarios

Hypervisor Device Emulation

Understand this scenario with real code like «hlv.b a0, (a1)».

Guest Memory Access

Understand this scenario with real code like «hlv.b a0, (a1)».

Virtualized Instruction Simulation

Understand this scenario with real code like «hlv.b a0, (a1)».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is I-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

Executing HLV/HLVX/HSV when virtualization mode V=1 raises a virtual-instruction exception.
U-mode execution is legal only when hstatus.HU=1; otherwise it raises illegal-instruction.
Access faults, guest-page faults, and page faults are still possible under the VS/G-stage translations.

FAQ

Is it a normal user-mode instruction?

No. These instructions are constrained by privilege level and extension support; user-mode legality must follow the privileged rules.

Does it replace ordinary memory fences?

No. Address translation, instruction fetch, and data-memory ordering use different fence/invalidation instructions.