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HLV.WU

RISC-V HLV.WU Instruction Details

Instruction ManualSYSTEM R-type fields

Hypervisor virtual-machine load of a zero-extended word using VS/VU effective privilege and two-stage translation.

Instruction Syntax

hlv.wu rd, (rs1)
Operand Breakdown
This is a SYSTEM R-type fields-format instruction. Confirm operand positions based on the assembly syntax.
HSystem & Privilege
Related Search Terms
HLV.WU instructionRISC-V HLV.WUhlv.wu syntaxhlv.wu encodinghlv.wu Hhlv.wu virtual loadhlv.wu zero extend

Instruction Behavior

HLV.WU is the H-extension virtual-machine load corresponding to LWU. It may execute in M-mode or HS-mode, or in U-mode when hstatus.HU=1. The explicit memory access uses effective privilege VU when hstatus.SPVP=0 and VS when hstatus.SPVP=1, with two-stage address translation. HLV.WU and HLV.D are not valid for RV32.

HLV.WU Decode And Execute Animation

Shows HLV.WU SYSTEM decoding, privilege checks, two-stage translation, and zero-extended writeback without modeling page walks or TLB implementation.

rd
rs1
hlv.wu
,(
)
31..25
24..20
19..15
14..12
11..7
6..0
0110100
funct7
00001
rs2[0]=U
01011
rs1/address
100
PRIVM
01010
rd
1110011
SYSTEM
Architectural Data Path
instruction
0x6815C573
decode
funct7=0110100, rs2=00001, funct3=100, rd=01010 -> HLV.WU
address
a1(x11) -> 0x0000000040001000 (no immediate offset)
privilege
HS: execution permitted
translation
VU effective privilege -> VS-stage -> G-stage; HS SUM ignored; MPRV is not used
load
32-bit 0x80000001 -> zero-extend -> 0x0000000080000001
state
Architectural state is not committed; the final rd state is shown only at writeback.
Architectural state is not committed; the final rd state is shown only at writeback.

This animation shows only official architectural conditions and outcomes; page walks, TLBs, caches, and platform exception handling are not modeled.

Quick Understanding & Search Notes

HLV.WU is the H-extension virtual-machine unsigned word load, loading through VS-stage and G-stage translation using the memory access's VS/VU effective privilege.

Execution permission, trap type, and state restoration depend on privilege level, relevant CSR bits, and extension presence.
H-extension memory/fence instructions involve VS-stage and G-stage two-stage translation.
RISC-V Privileged Architecture Manual, Hypervisor Extension

Common Usage Scenarios

Hypervisor Device Emulation

Understand this scenario with real code like «hlv.wu a0, (a1)».

Guest Memory Access

Understand this scenario with real code like «hlv.wu a0, (a1)».

Virtualized Instruction Simulation

Understand this scenario with real code like «hlv.wu a0, (a1)».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is SYSTEM R-type fields.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

Executing HLV/HLVX/HSV when virtualization mode V=1 raises a virtual-instruction exception.
U-mode execution is legal only when hstatus.HU=1; otherwise it raises illegal-instruction.
Access faults, guest-page faults, and page faults are still possible under the VS/G-stage translations.

FAQ

Is it a normal user-mode instruction?

No. These instructions are constrained by privilege level and extension support; user-mode legality must follow the privileged rules.

Does it replace ordinary memory fences?

No. Address translation, instruction fetch, and data-memory ordering use different fence/invalidation instructions.