Is it a normal user-mode instruction?
No. These instructions are constrained by privilege level and extension support; user-mode legality must follow the privileged rules.
HLV.D
RISC-V HLV.D Instruction Details
Instruction ManualI-typeHypervisor virtual-machine load of a doubleword using VS/VU effective privilege and two-stage translation.
Instruction Syntax
hlv.d rd, (rs1)
Operand Breakdown
Destination rd: general-purpose register receiving the result.
Source rs1: register holding the first operand.
Immediate imm: 12-bit signed value, sign-extended before operation with rs1.
HSystem & Privilege
Instruction Behavior
HLV.D is the H-extension virtual-machine load corresponding to LD. It may execute in M-mode or HS-mode, or in U-mode when hstatus.HU=1. The explicit memory access uses effective privilege VU when hstatus.SPVP=0 and VS when hstatus.SPVP=1, with two-stage address translation. HLV.WU and HLV.D are not valid for RV32.
Quick Understanding & Search Notes
HLV.D is the H-extension virtual-machine doubleword load, loading through VS-stage and G-stage translation using the memory access's VS/VU effective privilege.
Execution permission, trap type, and state restoration depend on privilege level, relevant CSR bits, and extension presence.
H-extension memory/fence instructions involve VS-stage and G-stage two-stage translation.
Common Usage Scenarios
Hypervisor Device Emulation
Understand this scenario with real code like «hlv.d a0, (a1)».
Guest Memory Access
Understand this scenario with real code like «hlv.d a0, (a1)».
Virtualized Instruction Simulation
Understand this scenario with real code like «hlv.d a0, (a1)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is I-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Executing HLV/HLVX/HSV when virtualization mode V=1 raises a virtual-instruction exception.
U-mode execution is legal only when hstatus.HU=1; otherwise it raises illegal-instruction.
Access faults, guest-page faults, and page faults are still possible under the VS/G-stage translations.
FAQ
Does it replace ordinary memory fences?
No. Address translation, instruction fetch, and data-memory ordering use different fence/invalidation instructions.