Is it a normal user-mode instruction?
No. These instructions are constrained by privilege level and extension support; user-mode legality must follow the privileged rules.
HLV.HU
RISC-V HLV.HU Instruction Details
Instruction ManualSYSTEM (R-type encoding)Hypervisor virtual-machine load of a zero-extended halfword using VS/VU effective privilege and two-stage translation.
Instruction Syntax
hlv.hu rd, (rs1)
Operand Breakdown
Destination rd: receives the zero-extended 16-bit loaded value; when rd=x0 the writeback value is discarded, but the explicit access still executes.
Address register rs1: directly supplies the explicit-access address; HLV.HU assembly has no offset immediate field.
The SYSTEM encoding fixes funct7=0110010, rs2=00001, funct3=100, and opcode=1110011; do not decode it as an ordinary I-type load.
HSystem & Privilege
Instruction Behavior
HLV.HU is the H-extension virtual-machine load corresponding to LHU. It reads a 16-bit halfword at the address in rs1 and zero-extends it to XLEN; the instruction has no immediate offset. It is valid only in M-mode, HS-mode, or U-mode with hstatus.HU=1. The explicit access uses the VU or VS effective privilege selected by hstatus.SPVP and two-stage translation.
HLV.HU Decode And Execute Animation
Shows HLV.HU SYSTEM decoding, privilege checks, two-stage translation, and zero-extended writeback without modeling page walks or TLB implementation.
rd
rs1
hlv.hu,()
31..25
24..20
19..15
14..12
11..7
6..0
0110010
funct7
00001
rs2[0]=U
01011
rs1/address
100
PRIVM
01010
rd
1110011
SYSTEM
Architectural Data Path
instruction
0x6415C573
decode
funct7=0110010, rs2=00001, funct3=100, rd=01010 -> HLV.HU
address
a1(x11) -> 0x0000000040001000 (no immediate offset)
privilege
HS: execution permitted
translation
VU effective privilege -> VS-stage -> G-stage; HS SUM ignored; MPRV is not used
load
16-bit 0x8001 -> zero-extend -> 0x0000000000008001
state
Architectural state is not committed; the final rd state is shown only at writeback.
Architectural state is not committed; the final rd state is shown only at writeback.
This animation shows only official architectural conditions and outcomes; page walks, TLBs, caches, and platform exception handling are not modeled.
Quick Understanding & Search Notes
HLV.HU is the H-extension virtual-machine unsigned halfword load, loading through VS-stage and G-stage translation using the memory access's VS/VU effective privilege.
Execution permission, trap type, and state restoration depend on privilege level, relevant CSR bits, and extension presence.
H-extension memory/fence instructions involve VS-stage and G-stage two-stage translation.
Common Usage Scenarios
Hypervisor Device Emulation
Understand this scenario with real code like «hlv.hu a0, (a1)».
Guest Memory Access
Understand this scenario with real code like «hlv.hu a0, (a1)».
Virtualized Instruction Simulation
Understand this scenario with real code like «hlv.hu a0, (a1)».
Pre-Use Checklist
Syntax Check
- Confirm the assembly syntax is hlv.hu rd, (rs1): rs1 supplies the address directly and there is no offset immediate.
- Confirm the SYSTEM encoding fixes rs2=00001, funct7=0110010, funct3=100, and opcode=1110011.
Semantic Check
- Confirm execution is in M/HS, or in U-mode with hstatus.HU=1; V=1 raises a virtual-instruction exception.
- Confirm the 16-bit load uses zero extension, and preserve handling for VS-stage/G-stage access faults, page faults, and guest-page faults.
Pitfalls / Common Confusions
Executing HLV/HLVX/HSV when virtualization mode V=1 raises a virtual-instruction exception.
U-mode execution is legal only when hstatus.HU=1; otherwise it raises illegal-instruction.
Access faults, guest-page faults, and page faults are still possible under the VS/G-stage translations.
FAQ
Does it replace ordinary memory fences?
No. Address translation, instruction fetch, and data-memory ordering use different fence/invalidation instructions.