Is it a normal user-mode instruction?
No. These instructions are constrained by privilege level and extension support; user-mode legality must follow the privileged rules.
HLVX.HU
RISC-V HLVX.HU Instruction Details
Instruction ManualI-typeHypervisor virtual-machine execute-permission halfword load; execute permission replaces read permission during translation.
Instruction Syntax
hlvx.hu rd, (rs1)
Operand Breakdown
Destination rd: general-purpose register receiving the result.
Source rs1: register holding the first operand.
Immediate imm: 12-bit signed value, sign-extended before operation with rs1.
HSystem & Privilege
Instruction Behavior
HLVX.HU is the H-extension virtual-machine load variant used for instruction-fetch emulation. It is like the corresponding HLV unsigned load except execute permission takes the place of read permission in both translation stages; the final physical memory attributes must allow both execute and read. It may execute in M-mode or HS-mode, or in U-mode when hstatus.HU=1.
Quick Understanding & Search Notes
HLVX.HU is the H-extension execute-permission halfword load for instruction-fetch emulation: translation permission checks use execute permission instead of read permission.
Execution permission, trap type, and state restoration depend on privilege level, relevant CSR bits, and extension presence.
H-extension memory/fence instructions involve VS-stage and G-stage two-stage translation.
Common Usage Scenarios
Hypervisor Device Emulation
Understand this scenario with real code like «hlvx.hu a0, (a1)».
Guest Memory Access
Understand this scenario with real code like «hlvx.hu a0, (a1)».
Virtualized Instruction Simulation
Understand this scenario with real code like «hlvx.hu a0, (a1)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is I-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
HLVX still raises load-style exceptions, not fetch exceptions.
HLVX does not override PMP; PMP execute-only memory can still cause an access fault.
Executing HLV/HLVX/HSV when virtualization mode V=1 raises a virtual-instruction exception.
FAQ
Does it replace ordinary memory fences?
No. Address translation, instruction fetch, and data-memory ordering use different fence/invalidation instructions.