Is it a normal user-mode instruction?
No. These instructions are constrained by privilege level and extension support; user-mode legality must follow the privileged rules.
HLVX.HU
RISC-V HLVX.HU Instruction Details
Instruction ManualSYSTEM R-type fieldsHypervisor virtual-machine execute-permission halfword load; execute permission replaces read permission during translation.
Instruction Syntax
hlvx.hu rd, (rs1)
Operand Breakdown
This is a SYSTEM R-type fields-format instruction. Confirm operand positions based on the assembly syntax.
HSystem & Privilege
Instruction Behavior
HLVX.HU is the H-extension virtual-machine load variant used for instruction-fetch emulation. It is like the corresponding HLV unsigned load except execute permission takes the place of read permission in both translation stages; the final physical memory attributes must allow both execute and read. It may execute in M-mode or HS-mode, or in U-mode when hstatus.HU=1.
HLVX.HU Decode And Execute Animation
Shows HLVX.HU SYSTEM decoding, privilege checks, two-stage translation, and zero-extended writeback without modeling page walks or TLB implementation.
rd
rs1
hlvx.hu,()
31..25
24..20
19..15
14..12
11..7
6..0
0110010
funct7
00011
rs2=00011 (HLVX)
01011
rs1/address
100
PRIVM
01010
rd
1110011
SYSTEM
Architectural Data Path
instruction
0x6435C573
decode
funct7=0110010, rs2=00011, funct3=100, rd=01010 -> HLVX.HU
address
a1(x11) -> 0x0000000040001000 (no immediate offset)
privilege
HS: execution permitted
translation
VU effective privilege -> VS-stage -> G-stage; HS SUM ignored; MPRV is not used; HLVX requires execute permission in both stages and final physical read+execute permission
load
16-bit 0x8001 -> zero-extend -> 0x0000000000008001
state
Architectural state is not committed; the final rd state is shown only at writeback.
Architectural state is not committed; the final rd state is shown only at writeback.
This animation shows only official architectural conditions and outcomes; page walks, TLBs, caches, and platform exception handling are not modeled.
Quick Understanding & Search Notes
HLVX.HU is the H-extension execute-permission halfword load for instruction-fetch emulation: translation permission checks use execute permission instead of read permission.
Execution permission, trap type, and state restoration depend on privilege level, relevant CSR bits, and extension presence.
H-extension memory/fence instructions involve VS-stage and G-stage two-stage translation.
Common Usage Scenarios
Hypervisor Device Emulation
Understand this scenario with real code like «hlvx.hu a0, (a1)».
Guest Memory Access
Understand this scenario with real code like «hlvx.hu a0, (a1)».
Virtualized Instruction Simulation
Understand this scenario with real code like «hlvx.hu a0, (a1)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is SYSTEM R-type fields.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
HLVX still raises load-style exceptions, not fetch exceptions.
HLVX does not override PMP; PMP execute-only memory can still cause an access fault.
Executing HLV/HLVX/HSV when virtualization mode V=1 raises a virtual-instruction exception.
FAQ
Does it replace ordinary memory fences?
No. Address translation, instruction fetch, and data-memory ordering use different fence/invalidation instructions.