Is it a normal user-mode instruction?
No. These instructions are constrained by privilege level and extension support; user-mode legality must follow the privileged rules.
HFENCE.GVMA
RISC-V HFENCE.GVMA Instruction Details
Instruction ManualR-typeHFENCE.GVMA is a G-stage address-translation fence: order/invalidate matching local-hart translations by guest physical address and VMID.
Instruction Syntax
hfence.gvma rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
HMemory Management
Instruction Behavior
HFENCE.GVMA is the Hypervisor extension G-stage memory-management fence. It guarantees that prior stores already visible to the current hart are ordered before subsequent implicit reads for G-stage address translation; if rs1 is not x0, it specifies one guest physical address shifted right by 2 bits, and if rs2 is not x0, it specifies one VMID. rs1=x0 means all guest physical addresses, and rs2=x0 means all VMIDs. It affects only the local hart; multi-hart systems need additional IPIs/remote execution.
Quick Understanding & Search Notes
HFENCE.GVMA is the H-extension G-stage address-translation fence, used to order updates to relevant two-stage translation structures with subsequent implicit translation on the local hart.
The instruction affects address translation or invalidation ordering; it is not a generic data-cache flush.
H-extension memory/fence instructions involve VS-stage and G-stage two-stage translation.
Common Usage Scenarios
Address & Pointer
Understand this scenario with real code like «hfence.gvma a1, a2».
Resource Management
Understand this scenario with real code like «hfence.gvma a1, a2».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Local hart only; multicore systems need IPIs or another mechanism to make other harts execute corresponding fences.
rs1 is a guest physical address shifted right by 2 bits, not a guest virtual address; rs2 is a VMID.
HFENCE.GVMA is valid only in M-mode or in HS-mode when mstatus.TVM=0.
FAQ
Does it replace ordinary memory fences?
No. Address translation, instruction fetch, and data-memory ordering use different fence/invalidation instructions.