Does SFENCE.VMA flush TLBs on all harts?
No. The official semantics apply to the current hart; a multi-hart system must make other harts execute the appropriate address-translation synchronization sequence.
SFENCE.VMA
RISC-V SFENCE.VMA Instruction Details
Instruction ManualR-typeSupervisor address-translation fence: rs1 selects virtual-address scope, rs2 selects ASID scope, synchronizing local page-table updates with later implicit translations.
Instruction Syntax
sfence.vma rs1, rs2
Operand Breakdown
Two integer source registers rs1/rs2; no rd or immediate operand. 32-bit SYSTEM, funct7=0001001, funct3=000 and rd=00000.
rs1=x0 selects any PTE level; non-x0 selects leaf PTEs for its VA mapping. rs2=x0 includes all ASIDs and globals; non-x0 excludes globals.
The x0 selector differs from zero in an ordinary register. High ASID bits are ignored by ASIDMAX/ASIDLEN rules.
Orders this hart's already-visible prior stores before selected later implicit references and invalidates corresponding translation entries; over-fencing is permitted.
At V=0, U-mode or S-mode/TVM=1 is illegal. Otherwise an invalid VA in non-x0 rs1 has no effect and no exception. H/VTVM adds rules.
PrivilegedMemory Management
Extension condition: Supervisor memory-management instruction; base permission statements below assume V=0. H adds VS/VU and VTVM rules.
Instruction Behavior
SFENCE.VMA orders prior stores already visible to this hart before selected implicit references to memory-management data structures by subsequent instructions on this hart, and invalidates selected address-translation cache entries. rs1=x0 covers PTEs at any level; a non-x0 rs1 covers only leaf PTEs for the mapping containing its virtual address. rs2=x0 covers all ASIDs including global mappings; non-x0 selects one ASID and excludes global mappings. The special all-scope selector is register x0, not a zero value in an ordinary register. An invalid VA in a non-x0 rs1 has no effect and raises no exception. Implementations may over-fence. The effect is local; other harts require separate synchronization. It does not replace data-memory FENCE or instruction-fetch synchronization.
SFENCE.VMA Decode And Translation-Fence Animation
Shows the R-type SYSTEM encoding, VA/ASID scope selected by rs1/rs2, and local-hart address-translation ordering.
rs1
rs2
sfence.vma
,
31..25
24..20
19..15
14..12
11..7
6..0
0001001
funct7
01011
rs2/ASID
01010
rs1/VA
000
funct3
00000
rd=x0
1110011
SYSTEM
Translation-Fence Scope
instruction
0x12B50073
opcode
1110011 -> SYSTEM
funct7
0001001 -> SFENCE.VMA
rs1
a0(x10) -> VA 0x0000000040001000
rs2
a1(x11) -> ASID 3 (raw 0x0000000000000003); globals not required
scope
a0(x10)=0x0000000040001000 (leaf PTEs only); a1(x11)=3 (raw 0x0000000000000003), global mappings not required
permission
S-mode may execute base SFENCE.VMA
ordering
prior stores visible to this hart ordered before selected later implicit references
complete
Not committed yet
This V=0 model assumes RV32/Sv32 or RV64/Sv39 and ASIDLEN=ASIDMAX (9/16); high ASID bits are ignored. Non-x0 rs1 selects leaf PTEs only; a zero value differs from x0. Equal nonzero source registers require equal initial values. The VA-valid checkbox supplies the semantic premise rather than deriving it from the number. Results preview the condition and commit only at Done. This animation covers U-mode illegal execution, S-mode execution with TVM=1, and the no-exception/no-effect branch for an invalid nonzero rs1 virtual address. It shows only local-hart semantics and does not model H/VTVM, TLB structures, caches, page-walk latency, or multi-hart shootdown protocols.
Quick Understanding & Search Notes
Supervisor address-translation fence: rs1 selects virtual-address scope, rs2 selects ASID scope, synchronizing local page-table updates with later implicit translations.
In the R-type SYSTEM encoding, funct7=0001001, funct3=000, rd=x0, and opcode=1110011.
rs1=x0 selects all virtual addresses; rs2=x0 selects all ASIDs and includes global mappings; a non-x0 rs2 is not required to order global mappings.
U-mode execution, and S-mode execution with TVM=1, raise illegal-instruction exceptions; a non-x0 rs1 containing an invalid VA has no effect and raises no exception.
The effect is local-hart address-translation ordering; multi-hart shootdown needs matching synchronization on other harts, and modified code still needs separate instruction-fetch synchronization, such as FENCE.I where applicable.
A non-x0 rs1 requires only the corresponding leaf-PTE scope. High rs2 bits are ignored according to ASIDMAX/ASIDLEN; ASID zero differs from rs2=x0.
Common Usage Scenarios
TLB sync after page table mod
With V=0, execution in S and TVM=0, sfence.vma x0, x0 covers this hart's PTEs at every level, all ASIDs and global mappings. Prior page-table stores must already be visible to this hart; other harts require separate synchronization.
Flush after munmap/mprotect
With V=0, execution in S and TVM=0, sfence.vma x0, x0 covers this hart's PTEs at every level, all ASIDs and global mappings. Prior page-table stores must already be visible to this hart; other harts require separate synchronization.
Address space switch
With V=0, execution in S and TVM=0, sfence.vma x0, x0 covers this hart's PTEs at every level, all ASIDs and global mappings. Prior page-table stores must already be visible to this hart; other harts require separate synchronization.
Pre-Use Checklist
Syntax Check
- Two integer source registers rs1/rs2; no rd or immediate operand. 32-bit SYSTEM, funct7=0001001, funct3=000 and rd=00000.
- rs1=x0 selects any PTE level; non-x0 selects leaf PTEs for its VA mapping. rs2=x0 includes all ASIDs and globals; non-x0 excludes globals.
Semantic Check
- The x0 selector differs from zero in an ordinary register. High ASID bits are ignored by ASIDMAX/ASIDLEN rules.
- Orders this hart's already-visible prior stores before selected later implicit references and invalidates corresponding translation entries; over-fencing is permitted.
- At V=0, U-mode or S-mode/TVM=1 is illegal. Otherwise an invalid VA in non-x0 rs1 has no effect and no exception. H/VTVM adds rules.
Pitfalls / Common Confusions
U-mode execution raises an illegal-instruction exception; in S-mode, mstatus.TVM=1 also raises an illegal-instruction exception.
Affects only the local hart; other harts need their own synchronization.
rs1=x0 means all virtual addresses; rs2=x0 means all ASIDs and includes global mappings, while a non-x0 rs2 is not required to order global mappings.
Implementations may over-fence; do not infer a concrete TLB structure or per-entry invalidation process from the architectural semantics.
It synchronizes address-translation caches/implicit translation observation, not the instruction cache; modified code still needs separate instruction-fetch synchronization, such as FENCE.I where applicable.
FAQ
What do rs1 and rs2 mean in SFENCE.VMA?
rs1 selects virtual-address scope, with x0 meaning all virtual addresses; rs2 selects ASID scope, with x0 meaning all ASIDs and including global mappings, while a non-x0 rs2 scope is not required to order global mappings.