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SFENCE.VMA

RISC-V SFENCE.VMA Instruction Details

Instruction ManualR-type

Sync virtual memory: invalidate local TLBs by rs1(VA) and rs2(ASID). rs1=x0=all, rs2=x0=all. Required after page table mod.

Instruction Syntax

sfence.vma rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
PrivilegedMemory Management
Related Search Terms
SFENCE.VMA instructionRISC-V SFENCE.VMAsfence.vma syntaxsfence.vma encodingsfence.vma privilegedsupervisor address-translation fence

Instruction Behavior

SFENCE.VMA synchronizes updates to memory-management data structures with subsequent implicit address translations by the current hart. rs1 selects a virtual address (x0 for all addresses), and rs2 selects an ASID (x0 for all ASIDs). It affects only the local hart; multi-hart TLB shootdown requires remote harts to execute the appropriate fence/invalidation sequence. It synchronizes address-translation caches, not the instruction cache; modified executable code still requires FENCE.I as specified by Zifencei.

Quick Understanding & Search Notes

SFENCE.VMA is a system-level instruction defined by the privileged architecture. This page covers architectural semantics only, not platform firmware policy.

The instruction affects address translation or invalidation ordering; it is not a generic data-cache flush.
Executing at an unsupported privilege level or without the required extension raises the specified exception.
RISC-V Privileged Architecture Manual, Supervisor-Level ISA

Common Usage Scenarios

TLB sync after page table mod

Understand this scenario with real code like «sfence.vma x0, x0 # Invalidate all TLB entries».

Flush after munmap/mprotect

Understand this scenario with real code like «sfence.vma x0, x0 # Invalidate all TLB entries».

Address space switch

Understand this scenario with real code like «sfence.vma x0, x0 # Invalidate all TLB entries».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is R-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

Normally legal only in S-mode or M-mode; U-mode execution raises an illegal-instruction exception.
Affects only the local hart; other harts need their own synchronization.
It synchronizes address-translation caches, not the instruction cache; modified code still needs FENCE.I.
rs1=x0 means all virtual addresses; rs2=x0 means all ASIDs.

FAQ

Is it a normal user-mode instruction?

No. These instructions are constrained by privilege level and extension support; user-mode legality must follow the privileged rules.

Does it replace ordinary memory fences?

No. Address translation, instruction fetch, and data-memory ordering use different fence/invalidation instructions.