Does SFENCE.VMA flush TLBs on all harts?
No. The official semantics apply to the current hart; a multi-hart system must make other harts execute the appropriate address-translation synchronization sequence.
SFENCE.VMA
RISC-V SFENCE.VMA Instruction Details
Instruction ManualR-typeSupervisor address-translation fence: rs1 selects virtual-address scope, rs2 selects ASID scope, synchronizing local page-table updates with later implicit translations.
Instruction Syntax
sfence.vma rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
PrivilegedMemory Management
Instruction Behavior
SFENCE.VMA synchronizes explicit updates to memory-management data structures by the current hart with later implicit address translations. rs1=x0 selects all virtual addresses; otherwise the value in rs1 selects one virtual address. rs2=x0 selects all ASIDs and includes global mappings; otherwise the value in rs2 selects one ASID and global mappings are not required to be ordered. If rs1 is nonzero but holds an invalid virtual address, the instruction has no effect and raises no exception. Implementations may perform a broader fence than requested. The instruction affects only the local hart; address-translation synchronization on other harts requires those harts to execute their own synchronization sequence. It is not a data-cache or instruction-cache flush instruction.
SFENCE.VMA Decode And Translation-Fence Animation
Shows the R-type SYSTEM encoding, VA/ASID scope selected by rs1/rs2, and local-hart address-translation ordering.
rs1
rs2
sfence.vma
,
31..25
24..20
19..15
14..12
11..7
6..0
0001001
funct7
01011
rs2/ASID
01010
rs1/VA
000
funct3
00000
rd=x0
1110011
SYSTEM
Translation-Fence Scope
instruction
0x12B50073
opcode
1110011 -> SYSTEM
funct7
0001001 -> SFENCE.VMA
rs1
a0(x10) -> VA 0x0000000040001000
rs2
a1(x11) -> ASID 3; globals not required
scope
a0(x10)=0x0000000040001000; a1(x11)=3, global mappings not required
permission
S-mode may execute base SFENCE.VMA
ordering
prior stores already visible to current hart's implicit translations
complete
subsequent implicit translations observe fence ordering for selected scope
This animation covers U-mode illegal execution, S-mode execution with TVM=1, and the no-exception/no-effect branch for an invalid nonzero rs1 virtual address. It shows only local-hart semantics and does not model H/VTVM, TLB structures, caches, page-walk latency, or multi-hart shootdown protocols.
Quick Understanding & Search Notes
SFENCE.VMA is not an ordinary memory fence or a portable TLB-structure model. It makes later implicit translations by the local hart observe prior memory-management updates for the selected VA/ASID scope; rs2=x0 includes global mappings, while a nonzero ASID scope is not required to include global mappings.
In the R-type SYSTEM encoding, funct7=0001001, funct3=000, rd=x0, and opcode=1110011.
rs1=x0 selects all virtual addresses; rs2=x0 selects all ASIDs and includes global mappings; rs2 nonzero is not required to order global mappings.
U-mode execution, and S-mode execution with TVM=1, raise illegal-instruction exceptions; a nonzero rs1 containing an invalid VA has no effect and raises no exception.
The effect is local-hart address-translation ordering; multi-hart shootdown needs matching synchronization on other harts, and modified code still needs FENCE.I.
Common Usage Scenarios
TLB sync after page table mod
Understand this scenario with real code like «sfence.vma x0, x0 # Fence all VA/ASID translations on this hart».
Flush after munmap/mprotect
Understand this scenario with real code like «sfence.vma x0, x0 # Fence all VA/ASID translations on this hart».
Address space switch
Understand this scenario with real code like «sfence.vma x0, x0 # Fence all VA/ASID translations on this hart».
Pre-Use Checklist
Syntax Check
- Verify rd, rs1, rs2 (and rs3) are valid GPRs.
- Confirm funct3 and funct7 encoding is correct.
Semantic Check
- Check if the result affects subsequent branches or address calculations.
- Ensure the rd register is not overwritten by another instruction.
Pitfalls / Common Confusions
U-mode execution raises an illegal-instruction exception; in S-mode, mstatus.TVM=1 also raises an illegal-instruction exception.
Affects only the local hart; other harts need their own synchronization.
rs1=x0 means all virtual addresses; rs2=x0 means all ASIDs and includes global mappings, while rs2 nonzero is not required to order global mappings.
Implementations may over-fence; do not infer a concrete TLB structure or per-entry invalidation process from the architectural semantics.
It synchronizes address-translation caches/implicit translation observation, not the instruction cache; modified code still needs FENCE.I.
FAQ
What do rs1 and rs2 mean in SFENCE.VMA?
rs1 selects virtual-address scope, with x0 meaning all virtual addresses; rs2 selects ASID scope, with x0 meaning all ASIDs and including global mappings, while a nonzero rs2 scope is not required to order global mappings.