Does SFENCE.W.INVAL perform invalidation?
It is an ordering boundary, not the VA/ASID-scoped invalidation instruction; invalidation is performed by SINVAL.VMA, or by HINVAL.* when H is implemented.
SFENCE.W.INVAL
RISC-V SFENCE.W.INVAL Instruction Details
Instruction ManualR-typeSvinval leading ordering instruction: orders prior stores already visible to the current hart before subsequent SINVAL.VMA invalidations; with H, it also combines with HINVAL.*.
Instruction Syntax
sfence.w.inval
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
PrivilegedSvinvalMemory Management
Instruction Behavior
SFENCE.W.INVAL is the leading ordering boundary for a split Svinval invalidation sequence and has no explicit assembly operands. It orders previous stores already visible to the current hart before subsequent SINVAL.VMA instructions executed by that hart. With H, it also combines with HINVAL.VVMA or HINVAL.GVMA. It does not perform VA/ASID-scoped invalidation and is not a generic data-cache flush; the typical sequence is SFENCE.W.INVAL -> one or more SINVAL.VMA -> SFENCE.INVAL.IR.
SFENCE.W.INVAL Decode And Svinval Animation
Shows the fixed SYSTEM encoding and ordering boundary in an Svinval sequence; this instruction has no explicit assembly operands.
sfence.w.inval
no explicit operands
Execution ContextSvinvalThis ordering boundary applies to the current hart's invalidation sequence.
31..20
19..15
14..12
11..7
6..0
000110000000
funct12
00000
rs1=x0
000
funct3
00000
rd=x0
1110011
SYSTEM
Svinval Sequence State
instruction
0x18000073
opcode
1110011 -> SYSTEM
funct12
000110000000 -> SFENCE.W.INVAL
operands
rd=x0, rs1=x0, no assembly operands
sequence
SFENCE.W.INVAL -> SINVAL.VMA (H: HINVAL.*)... -> SFENCE.INVAL.IR
ordering
prior visible stores -> later SINVAL.VMA (and HINVAL with H)
This animation shows only the local-hart invalidation/ordering relation defined by the privileged architecture; it does not simulate TLB structures, cache flushes, page-walk latency, IPIs, or OS shootdown protocols.
Quick Understanding & Search Notes
SFENCE.W.INVAL is the opening bracket of an Svinval sequence: it orders stores already visible to the current hart before later invalidation instructions.
The instruction has no explicit assembly operands; rs1 and rd are fixed to x0 in the encoding.
It establishes the ordering boundary from prior visible stores to later SINVAL.VMA instructions; with H it also combines with HINVAL.*.
It does not select a VA/ASID scope and does not model caches or shootdown protocols.
Common Usage Scenarios
Memory Management
Understand this scenario with real code like «sfence.w.inval».
Translation Invalidation
Understand this scenario with real code like «sfence.w.inval».
Translation Cache Invalidation
Understand this scenario with real code like «sfence.w.inval».
Svinval Sequence
Understand this scenario with real code like «sfence.w.inval».
Pre-Use Checklist
Syntax Check
- Verify rd, rs1, rs2 (and rs3) are valid GPRs.
- Confirm funct3 and funct7 encoding is correct.
Semantic Check
- Check if the result affects subsequent branches or address calculations.
- Ensure the rd register is not overwritten by another instruction.
Pitfalls / Common Confusions
U-mode execution raises illegal-instruction; VU-mode execution raises virtual-instruction.
Unaffected by mstatus.TVM and hstatus.VTVM; permitted in S-mode and VS-mode.
The instruction has no explicit assembly operands; rs1 and rd fields are fixed to x0.
Orders prior visible stores before subsequent SINVAL.VMA invalidations; HINVAL.* applies only with H; it does not itself select a VA/ASID invalidation range.
Do not treat it as a data-cache flush or an OS shootdown protocol.
FAQ
Why does it have no operands?
It describes a sequence ordering boundary, not an address or ASID scope; the relevant register fields in the encoding are fixed to x0.