Does SFENCE.W.INVAL perform invalidation?
No. SINVAL.VMA performs invalidation; with H, HINVAL.* can do so.
SFENCE.W.INVAL
RISC-V SFENCE.W.INVAL Instruction Details
Instruction ManualSYSTEM R-type fieldsSvinval leading ordering instruction: orders prior stores already visible to the current hart before subsequent SINVAL.VMA invalidations; with H, it also combines with HINVAL.*.
Instruction Syntax
sfence.w.inval
Operand Breakdown
Svinval 1.0; RV32/RV64; 32-bit SYSTEM R-type fields, funct7=0001100, rs2=00000, rs1=00000, funct3=000, rd=00000, opcode=1110011.
No explicit assembly operands; rs2 is a fixed selector, not an x0/x1 read. No VA/ASID selection or general-register writeback.
Orders prior stores already visible to this hart before subsequent SINVAL.VMA by the same hart.
U-mode raises illegal-instruction; VU-mode raises virtual-instruction. S/VS may execute regardless of TVM/VTVM. With H, also combines with HINVAL.VVMA/GVMA.
PrivilegedSvinvalMemory Management
Instruction Behavior
SFENCE.W.INVAL is the leading ordering boundary for a split Svinval invalidation sequence and has no explicit assembly operands. It orders previous stores already visible to the current hart before subsequent SINVAL.VMA instructions executed by that hart. With H, it also combines with HINVAL.VVMA or HINVAL.GVMA. It does not perform VA/ASID-scoped invalidation and is not a generic data-cache flush; the typical sequence is SFENCE.W.INVAL -> one or more SINVAL.VMA -> SFENCE.INVAL.IR.
SFENCE.W.INVAL Decode And Svinval Animation
Shows the fixed SYSTEM encoding and ordering boundary in an Svinval sequence; this instruction has no explicit assembly operands.
sfence.w.inval
no explicit operands
Execution ContextSvinvalThis ordering boundary applies to the current hart's invalidation sequence.Assumes Svinval; VS/VU branches also assume H. TVM/VTVM do not restrict these ordering instructions. Steps are teaching views.
31..20
19..15
14..12
11..7
6..0
000110000000
funct12
00000
rs1=x0
000
funct3
00000
rd=x0
1110011
SYSTEM
Svinval Sequence State
instruction
0x18000073
opcode
1110011 -> SYSTEM
funct12
000110000000 -> SFENCE.W.INVAL
operands
rd=x0, rs1=x0, no assembly operands
sequence
SFENCE.W.INVAL -> SINVAL.VMA (H: HINVAL.*)... -> SFENCE.INVAL.IR
privilege
HS: execution permitted
ordering
pending ordering completion
This animation shows only the local-hart invalidation/ordering relation defined by the privileged architecture; it does not simulate TLB structures, cache flushes, page-walk latency, IPIs, or OS shootdown protocols.
Quick Understanding & Search Notes
SFENCE.W.INVAL is the opening bracket of an Svinval sequence: it orders stores already visible to the current hart before later invalidation instructions.
No operands; rs1=rd=x0, rs2=00000 is a fixed selector.
Orders prior visible stores before later SINVAL.VMA on this hart. With H, also combines with HINVAL.*.
No VA/ASID scope selection or cache flush.
U-mode: illegal-instruction; VU-mode: virtual-instruction. S/VS permitted regardless of TVM/VTVM.
Common Usage Scenarios
Memory Management
Assume Svinval, S-mode, and one hart executing SFENCE.W.INVAL → SINVAL.VMA x0,x0 → SFENCE.INVAL.IR in order. The leading fence orders prior stores already visible to that hart; the trailing fence orders later implicit page-table references. Neither boundary selects an invalidation scope or writes a general register.
Translation Invalidation
Assume Svinval, S-mode, and one hart executing SFENCE.W.INVAL → SINVAL.VMA x0,x0 → SFENCE.INVAL.IR in order. The leading fence orders prior stores already visible to that hart; the trailing fence orders later implicit page-table references. Neither boundary selects an invalidation scope or writes a general register.
Translation Cache Invalidation
Assume Svinval, S-mode, and one hart executing SFENCE.W.INVAL → SINVAL.VMA x0,x0 → SFENCE.INVAL.IR in order. The leading fence orders prior stores already visible to that hart; the trailing fence orders later implicit page-table references. Neither boundary selects an invalidation scope or writes a general register.
Svinval Sequence
Assume Svinval, S-mode, and one hart executing SFENCE.W.INVAL → SINVAL.VMA x0,x0 → SFENCE.INVAL.IR in order. The leading fence orders prior stores already visible to that hart; the trailing fence orders later implicit page-table references. Neither boundary selects an invalidation scope or writes a general register.
Pre-Use Checklist
Syntax Check
- Svinval 1.0; RV32/RV64; 32-bit SYSTEM R-type fields, funct7=0001100, rs2=00000, rs1=00000, funct3=000, rd=00000, opcode=1110011.
- No explicit assembly operands; rs2 is a fixed selector, not an x0/x1 read. No VA/ASID selection or general-register writeback.
Semantic Check
- Orders prior stores already visible to this hart before subsequent SINVAL.VMA by the same hart.
- U-mode raises illegal-instruction; VU-mode raises virtual-instruction. S/VS may execute regardless of TVM/VTVM. With H, also combines with HINVAL.VVMA/GVMA.
Pitfalls / Common Confusions
U-mode execution raises illegal-instruction; VU-mode execution raises virtual-instruction.
Unaffected by mstatus.TVM and hstatus.VTVM; permitted in S-mode and VS-mode.
The instruction has no explicit assembly operands; rs1 and rd fields are fixed to x0.
Orders prior visible stores before subsequent SINVAL.VMA invalidations; HINVAL.* applies only with H; it does not itself select a VA/ASID invalidation range.
Do not treat it as a data-cache flush or an OS shootdown protocol.
FAQ
Why does it have no operands?
It orders the sequence rather than selecting an address or ASID; rs1/rd are fixed to x0.