Is it a normal user-mode instruction?
No. These instructions are constrained by privilege level and extension support; user-mode legality must follow the privileged rules.
SFENCE.W.INVAL
RISC-V SFENCE.W.INVAL Instruction Details
Instruction ManualR-typeSvinval ordering instruction: orders prior visible stores before subsequent SINVAL/HINVAL invalidations.
Instruction Syntax
sfence.w.inval
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
PrivilegedSvinvalMemory Management
Instruction Behavior
SFENCE.W.INVAL is a Svinval ordering instruction with no architectural operands. It guarantees that previous stores already visible to the current RISC-V hart are ordered before subsequent SINVAL.VMA, HINVAL.VVMA, or HINVAL.GVMA instructions executed by that hart. The typical sequence is SFENCE.W.INVAL -> a series of SINVAL/HINVAL instructions -> SFENCE.INVAL.IR.
Quick Understanding & Search Notes
SFENCE.W.INVAL is a system-level instruction defined by the privileged architecture. This page covers architectural semantics only, not platform firmware policy.
The instruction affects address translation or invalidation ordering; it is not a generic data-cache flush.
Executing at an unsupported privilege level or without the required extension raises the specified exception.
Common Usage Scenarios
Memory Management
Understand this scenario with real code like «sfence.w.inval».
Translation Invalidation
Understand this scenario with real code like «sfence.w.inval».
TLB Shootdown
Understand this scenario with real code like «sfence.w.inval».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
U-mode execution raises illegal-instruction; VU-mode execution raises virtual-instruction.
Unaffected by mstatus.TVM and hstatus.VTVM; permitted in S-mode and VS-mode.
Orders prior visible stores before subsequent SINVAL/HINVAL invalidations.
FAQ
Does it replace ordinary memory fences?
No. Address translation, instruction fetch, and data-memory ordering use different fence/invalidation instructions.