Is rs2 a VMID for HINVAL.VVMA?
No. rs2 is ASID; the current VMID comes from virtualization context.
HINVAL.VVMA
RISC-V HINVAL.VVMA Instruction Details
Instruction ManualSYSTEM R-typeSvinval/H VS-stage translation invalidation: rs1 selects guest virtual address, rs2 selects ASID, and current VMID comes from virtualization context.
Instruction Syntax
hinval.vvma rs1, rs2
Operand Breakdown
rs1: supplies the virtual address; rs1=x0 selects all relevant virtual addresses.
rs2: supplies the ASID; rs2=x0 selects all ASIDs.
This SYSTEM R-type instruction has no rd writeback or immediate field; rs1/rs2 only limit the invalidation scope.
HSvinvalMemory Management
Instruction Behavior
HINVAL.VVMA is the Hypervisor + Svinval VS-stage address-translation-cache invalidation instruction. It invalidates VS-stage translation-cache entries matching the guest virtual address in rs1 and ASID in rs2; rs1=x0 selects all guest virtual addresses, and rs2=x0 selects all ASIDs. The current VMID comes from virtualization context rather than rs2. It does not guarantee full ordering alone; SFENCE.W.INVAL and SFENCE.INVAL.IR supply the sequence ordering boundaries. Implementations may use the full matching HFENCE.
HINVAL.VVMA Hypervisor Translation Decode Animation
Svinval/H VS-stage invalidation: shows SYSTEM encoding, rs1/rs2 scope selection, and Svinval/H invalidation without modeling TLB or cache implementation.
rs1
rs2
hinval.vvma
,
This example assumes H and Svinval, equal host/guest XLEN, valid addresses, and maximum implemented ID widths (RV32: ASID 9/VMID 7; RV64: ASID 16/VMID 14). High rs2 bits above the ID width are ignored; software should zero reserved high bits. Implementations may fence/invalidate a broader scope. Current VMID comes from hgatp.VMID; a specified ASID need not invalidate global mappings.
31..25
24..20
19..15
14..12
11..7
6..0
0010011
funct7
01011
rs2/ASID
01010
rs1/GVA
000
funct3
00000
rd=x0
1110011
SYSTEM
Hypervisor Translation State
instruction
0x26B50073
opcode
1110011 -> SYSTEM
funct7
0010011 -> HINVAL.VVMA
rs1
a0(x10) -> GVA 0x0000000040001000
rs2
a1(x11)=0x0000000000000003 -> ASID 3
VMID
current VMID 7 from virtualization context
scope
a0(x10)=0x0000000040001000; a1(x11)=0x0000000000000003 -> ASID 3, current VMID=7; global mappings not required
permission
HS; TVM does not affect this instruction
invalidate
Fence/invalidation effect not performed yet
complete
Fence/invalidation effect not performed yet
This animation shows only the local-hart translation fence/invalidation semantics defined by the privileged architecture; it does not show OS shootdown protocols, TLB structures, cache flushes, page-walk latency, or platform interrupt mechanisms.
Quick Understanding & Search Notes
HINVAL.VVMA is the VS-stage invalidation action inside a split-fence sequence: rs1 selects guest virtual address, rs2 selects ASID, and current VMID does not come from rs2.
funct7=0010011, funct3=000, rd=x0, opcode=1110011 identify HINVAL.VVMA.
HINVAL.VVMA follows HFENCE.VVMA scope selection: rs1 is guest virtual address, rs2 is ASID.
The typical split-fence relation is SFENCE.W.INVAL -> one or more HINVAL/SINVAL -> SFENCE.INVAL.IR.
Common Usage Scenarios
VS-stage invalidation sequence
Understand this scenario with real code like «sfence.w.inval hinval.vvma a1, a2 # a1 = guest VA; a2 = ASID sfence.inval.ir».
Pre-Use Checklist
Syntax Check
- Confirm the assembly has only rs1 and rs2: this SYSTEM R-type instruction has no rd writeback or immediate field.
- Confirm the rs1/rs2 scope: rs1=x0 selects all virtual addresses, and rs2=x0 selects all ASIDs.
Semantic Check
- Confirm execution is in a permitted privilege state; when an illegal-instruction or virtual-instruction exception occurs, do not treat the invalidation effect as complete.
- Confirm rs1/rs2 only narrow the VVMA invalidation scope; x0/x0 selects the full scope.
Pitfalls / Common Confusions
rs1≠x0 selects a guest virtual address; rs2 selects ASID, while hgatp.VMID supplies the current VMID.
Valid only in M/HS-mode; TVM and VTVM do not trap this instruction. V=1 raises virtual-instruction; U-mode raises illegal-instruction.
Local-hart effect; implementations may cover a broader scope. This is not a generic data-cache flush.
For rs2≠x0, zero reserved high bits; bits above the implemented ID width are ignored. A specified ASID need not cover global mappings.
Requires H and Svinval; SFENCE.W.INVAL → HINVAL → SFENCE.INVAL.IR in order supplies the matching HFENCE ordering boundaries.
FAQ
How does HINVAL.VVMA differ from HFENCE.VVMA?
HINVAL.VVMA alone does not guarantee full ordering; split fences supply it. HFENCE.VVMA is the full fence, and implementations may use it for HINVAL.