Is rs2 a VMID for HINVAL.VVMA?
No. rs2 is ASID; the current VMID comes from virtualization context.
HINVAL.VVMA
RISC-V HINVAL.VVMA Instruction Details
Instruction ManualR-typeSvinval/H VS-stage translation invalidation: rs1 selects guest virtual address, rs2 selects ASID, and current VMID comes from virtualization context.
Instruction Syntax
hinval.vvma rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
HSvinvalMemory Management
Instruction Behavior
HINVAL.VVMA is the Hypervisor + Svinval VS-stage address-translation-cache invalidation instruction. It invalidates VS-stage translation-cache entries matching the guest virtual address in rs1 and ASID in rs2; rs1=x0 selects all guest virtual addresses, and rs2=x0 selects all ASIDs. The current VMID comes from virtualization context rather than rs2. It performs invalidation only; ordering is supplied by SFENCE.W.INVAL and SFENCE.INVAL.IR split fences.
HINVAL.VVMA Hypervisor Translation Decode Animation
Svinval/H VS-stage invalidation: shows SYSTEM encoding, rs1/rs2 scope selection, and Svinval/H invalidation without modeling TLB or cache implementation.
rs1
rs2
hinval.vvma
,
31..25
24..20
19..15
14..12
11..7
6..0
0010011
funct7
01011
rs2/ASID
01010
rs1/GVA
000
funct3
00000
rd=x0
1110011
SYSTEM
Hypervisor Translation State
instruction
0x26B50073
opcode
1110011 -> SYSTEM
funct7
0010011 -> HINVAL.VVMA
rs1
a0(x10) -> GVA 0x0000000040001000
rs2
a1(x11) -> ASID 3
VMID
current VMID 7 from virtualization context
scope
a0(x10)=0x0000000040001000; a1(x11)=ASID 3, current VMID=7
invalidate
invalidate matching VS-stage translation-cache entries
complete
selected VS-stage translation-cache entries invalidated
This animation shows only the local-hart translation fence/invalidation semantics defined by the privileged architecture; it does not show OS shootdown protocols, TLB structures, cache flushes, page-walk latency, or platform interrupt mechanisms.
Quick Understanding & Search Notes
HINVAL.VVMA is the VS-stage invalidation action inside a split-fence sequence: rs1 selects guest virtual address, rs2 selects ASID, and current VMID does not come from rs2.
funct7=0010011, funct3=000, rd=x0, opcode=1110011 identify HINVAL.VVMA.
HINVAL.VVMA follows HFENCE.VVMA scope selection: rs1 is guest virtual address, rs2 is ASID.
The typical split-fence relation is SFENCE.W.INVAL -> one or more HINVAL/SINVAL -> SFENCE.INVAL.IR.
Common Usage Scenarios
Svinval sequence
Understand this scenario with real code like «hinval.vvma a1, a2 # a1 = guest virtual address; a2 = ASID».
VS-stage invalidation
Understand this scenario with real code like «hinval.vvma a1, a2 # a1 = guest virtual address; a2 = ASID».
Virtualization TLB shootdown
Understand this scenario with real code like «hinval.vvma a1, a2 # a1 = guest virtual address; a2 = ASID».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Requires H plus Svinval; permissions/exceptions correspond to HFENCE.VVMA.
rs1 specifies guest virtual address; do not confuse it with HINVAL.GVMA GPA>>2.
rs2 specifies ASID, not VMID; the current VMID comes from virtualization context.
It performs invalidation only and does not supply complete ordering; use SFENCE.W.INVAL and SFENCE.INVAL.IR for the split-fence sequence.
Do not read HINVAL.VVMA as a data-cache flush or concrete TLB-entry walk.
FAQ
How does HINVAL.VVMA differ from HFENCE.VVMA?
HINVAL.VVMA performs VS-stage invalidation with ordering supplied by a split-fence sequence; HFENCE.VVMA is the full VS-stage translation fence.