Is it a normal user-mode instruction?
No. These instructions are constrained by privilege level and extension support; user-mode legality must follow the privileged rules.
HINVAL.VVMA
RISC-V HINVAL.VVMA Instruction Details
Instruction ManualR-typeSvinval/H VS-stage invalidation: invalidate by guest virtual address and ASID, with ordering supplied by split fences.
Instruction Syntax
hinval.vvma rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
HSvinvalMemory Management
Instruction Behavior
HINVAL.VVMA is the Hypervisor + Svinval VS-stage address-translation-cache invalidation instruction. It invalidates VS-stage translation-cache entries matching the guest virtual address in rs1 and ASID in rs2; rs1=x0 means all guest virtual addresses, and rs2=x0 means all ASIDs. The current VMID comes from the virtualization context rather than rs2. It performs invalidation only; ordering is supplied by SFENCE.W.INVAL and SFENCE.INVAL.IR.
Quick Understanding & Search Notes
HINVAL.VVMA is the Svinval/H VS-stage address-translation invalidation; it performs invalidation only, while SFENCE.W.INVAL and SFENCE.INVAL.IR supply split-fence ordering.
The instruction affects address translation or invalidation ordering; it is not a generic data-cache flush.
H-extension memory/fence instructions involve VS-stage and G-stage two-stage translation.
Common Usage Scenarios
Memory Management
Understand this scenario with real code like «hinval.vvma a1, a2».
Virtualization
Understand this scenario with real code like «hinval.vvma a1, a2».
TLB Shootdown
Understand this scenario with real code like «hinval.vvma a1, a2».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Requires H plus Svinval, with permissions/exceptions corresponding to HFENCE.VVMA.
rs1 specifies a guest virtual address; rs2 specifies an ASID, not a VMID.
Execution in VS-mode or VU-mode raises a virtual-instruction exception.
Use with SFENCE.W.INVAL and SFENCE.INVAL.IR to obtain split-fence ordering.
FAQ
Does it replace ordinary memory fences?
No. Address translation, instruction fetch, and data-memory ordering use different fence/invalidation instructions.