Is SFENCE.INVAL.IR the same as FENCE.I?
No. This fence orders page-table references; FENCE.I synchronizes instruction fetching.
SFENCE.INVAL.IR
RISC-V SFENCE.INVAL.IR Instruction Details
Instruction ManualSYSTEM R-type fieldsSvinval trailing ordering instruction: orders prior SINVAL.VMA invalidations before subsequent implicit page-table references; with H, it also combines with HINVAL.*.
Instruction Syntax
sfence.inval.ir
Operand Breakdown
Svinval 1.0; RV32/RV64; 32-bit SYSTEM R-type fields, funct7=0001100, rs2=00001, rs1=00000, funct3=000, rd=00000, opcode=1110011.
No explicit assembly operands; rs2 is a fixed selector, not an x0/x1 read. No VA/ASID selection or general-register writeback.
Orders prior SINVAL.VMA by this hart before its subsequent implicit references to memory-management data structures.
U-mode raises illegal-instruction; VU-mode raises virtual-instruction. S/VS may execute regardless of TVM/VTVM. With H, also combines with HINVAL.VVMA/GVMA.
PrivilegedSvinvalMemory Management
Instruction Behavior
SFENCE.INVAL.IR is the trailing ordering boundary for a split Svinval invalidation sequence and has no explicit assembly operands. It orders prior SINVAL.VMA invalidations by the current hart before subsequent implicit references by that hart to memory-management data structures. With H, it also combines with HINVAL.VVMA or HINVAL.GVMA. It does not select a VA/ASID invalidation scope and is not an instruction-cache flush; the typical sequence is SFENCE.W.INVAL -> one or more SINVAL.VMA -> SFENCE.INVAL.IR.
SFENCE.INVAL.IR Decode And Svinval Animation
Shows the fixed SYSTEM encoding and ordering boundary in an Svinval sequence; this instruction has no explicit assembly operands.
sfence.inval.ir
no explicit operands
Execution ContextSvinvalThis ordering boundary applies to the current hart's invalidation sequence.Assumes Svinval; VS/VU branches also assume H. TVM/VTVM do not restrict these ordering instructions. Steps are teaching views.
31..20
19..15
14..12
11..7
6..0
000110000001
funct12
00000
rs1=x0
000
funct3
00000
rd=x0
1110011
SYSTEM
Svinval Sequence State
instruction
0x18100073
opcode
1110011 -> SYSTEM
funct12
000110000001 -> SFENCE.INVAL.IR
operands
rd=x0, rs1=x0, no assembly operands
sequence
SFENCE.W.INVAL -> SINVAL.VMA (H: HINVAL.*)... -> SFENCE.INVAL.IR
privilege
HS: execution permitted
ordering
pending ordering completion
This animation shows only the local-hart invalidation/ordering relation defined by the privileged architecture; it does not simulate TLB structures, cache flushes, page-walk latency, IPIs, or OS shootdown protocols.
Quick Understanding & Search Notes
SFENCE.INVAL.IR is the closing bracket of an Svinval sequence: it orders prior invalidations before later implicit page-table references.
No operands; rs1=rd=x0, rs2=00001 is a fixed selector.
Orders prior SINVAL.VMA before later implicit page-table references on this hart. With H, also combines with HINVAL.*.
Not FENCE.I or an instruction-cache flush.
U-mode: illegal-instruction; VU-mode: virtual-instruction. S/VS permitted regardless of TVM/VTVM.
Common Usage Scenarios
Memory Management
Assume Svinval, S-mode, and one hart executing SFENCE.W.INVAL → SINVAL.VMA x0,x0 → SFENCE.INVAL.IR in order. The leading fence orders prior stores already visible to that hart; the trailing fence orders later implicit page-table references. Neither boundary selects an invalidation scope or writes a general register.
Translation Invalidation
Assume Svinval, S-mode, and one hart executing SFENCE.W.INVAL → SINVAL.VMA x0,x0 → SFENCE.INVAL.IR in order. The leading fence orders prior stores already visible to that hart; the trailing fence orders later implicit page-table references. Neither boundary selects an invalidation scope or writes a general register.
Translation Cache Invalidation
Assume Svinval, S-mode, and one hart executing SFENCE.W.INVAL → SINVAL.VMA x0,x0 → SFENCE.INVAL.IR in order. The leading fence orders prior stores already visible to that hart; the trailing fence orders later implicit page-table references. Neither boundary selects an invalidation scope or writes a general register.
Svinval Sequence
Assume Svinval, S-mode, and one hart executing SFENCE.W.INVAL → SINVAL.VMA x0,x0 → SFENCE.INVAL.IR in order. The leading fence orders prior stores already visible to that hart; the trailing fence orders later implicit page-table references. Neither boundary selects an invalidation scope or writes a general register.
Pre-Use Checklist
Syntax Check
- Svinval 1.0; RV32/RV64; 32-bit SYSTEM R-type fields, funct7=0001100, rs2=00001, rs1=00000, funct3=000, rd=00000, opcode=1110011.
- No explicit assembly operands; rs2 is a fixed selector, not an x0/x1 read. No VA/ASID selection or general-register writeback.
Semantic Check
- Orders prior SINVAL.VMA by this hart before its subsequent implicit references to memory-management data structures.
- U-mode raises illegal-instruction; VU-mode raises virtual-instruction. S/VS may execute regardless of TVM/VTVM. With H, also combines with HINVAL.VVMA/GVMA.
Pitfalls / Common Confusions
U-mode execution raises illegal-instruction; VU-mode execution raises virtual-instruction.
Unaffected by mstatus.TVM and hstatus.VTVM; permitted in S-mode and VS-mode.
The instruction has no explicit assembly operands; rs1 and rd fields are fixed to x0.
Orders prior SINVAL.VMA invalidations before subsequent implicit page-table references; HINVAL.* applies only with H.
Do not treat it as FENCE.I, an instruction-cache flush, or a concrete page-table walk.
FAQ
Why is it placed at the end of the sequence?
It orders prior SINVAL.VMA before later implicit memory-management references; with H, also combines with HINVAL.*.