Is SFENCE.INVAL.IR the same as FENCE.I?
No. SFENCE.INVAL.IR orders implicit page-table references after Svinval invalidations; FENCE.I has different instruction-fetch synchronization semantics.
SFENCE.INVAL.IR
RISC-V SFENCE.INVAL.IR Instruction Details
Instruction ManualR-typeSvinval trailing ordering instruction: orders prior SINVAL.VMA invalidations before subsequent implicit page-table references; with H, it also combines with HINVAL.*.
Instruction Syntax
sfence.inval.ir
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
PrivilegedSvinvalMemory Management
Instruction Behavior
SFENCE.INVAL.IR is the trailing ordering boundary for a split Svinval invalidation sequence and has no explicit assembly operands. It orders prior SINVAL.VMA invalidations by the current hart before subsequent implicit references by that hart to memory-management data structures. With H, it also combines with HINVAL.VVMA or HINVAL.GVMA. It does not select a VA/ASID invalidation scope and is not an instruction-cache flush; the typical sequence is SFENCE.W.INVAL -> one or more SINVAL.VMA -> SFENCE.INVAL.IR.
SFENCE.INVAL.IR Decode And Svinval Animation
Shows the fixed SYSTEM encoding and ordering boundary in an Svinval sequence; this instruction has no explicit assembly operands.
sfence.inval.ir
no explicit operands
Execution ContextSvinvalThis ordering boundary applies to the current hart's invalidation sequence.
31..20
19..15
14..12
11..7
6..0
000110000001
funct12
00000
rs1=x0
000
funct3
00000
rd=x0
1110011
SYSTEM
Svinval Sequence State
instruction
0x18100073
opcode
1110011 -> SYSTEM
funct12
000110000001 -> SFENCE.INVAL.IR
operands
rd=x0, rs1=x0, no assembly operands
sequence
SFENCE.W.INVAL -> SINVAL.VMA (H: HINVAL.*)... -> SFENCE.INVAL.IR
ordering
prior SINVAL.VMA (and HINVAL with H) -> later implicit page-table references
This animation shows only the local-hart invalidation/ordering relation defined by the privileged architecture; it does not simulate TLB structures, cache flushes, page-walk latency, IPIs, or OS shootdown protocols.
Quick Understanding & Search Notes
SFENCE.INVAL.IR is the closing bracket of an Svinval sequence: it orders prior invalidations before later implicit page-table references.
The instruction has no explicit assembly operands; rs1 and rd are fixed to x0 in the encoding.
It establishes the ordering boundary from prior SINVAL.VMA to later implicit page-table references; with H it also combines with HINVAL.*.
It is not FENCE.I and does not mean a generic instruction-cache flush.
Common Usage Scenarios
Memory Management
Understand this scenario with real code like «sfence.inval.ir».
Translation Invalidation
Understand this scenario with real code like «sfence.inval.ir».
Translation Cache Invalidation
Understand this scenario with real code like «sfence.inval.ir».
Svinval Sequence
Understand this scenario with real code like «sfence.inval.ir».
Pre-Use Checklist
Syntax Check
- Verify rd, rs1, rs2 (and rs3) are valid GPRs.
- Confirm funct3 and funct7 encoding is correct.
Semantic Check
- Check if the result affects subsequent branches or address calculations.
- Ensure the rd register is not overwritten by another instruction.
Pitfalls / Common Confusions
U-mode execution raises illegal-instruction; VU-mode execution raises virtual-instruction.
Unaffected by mstatus.TVM and hstatus.VTVM; permitted in S-mode and VS-mode.
The instruction has no explicit assembly operands; rs1 and rd fields are fixed to x0.
Orders prior SINVAL.VMA invalidations before subsequent implicit page-table references; HINVAL.* applies only with H.
Do not treat it as FENCE.I, an instruction-cache flush, or a concrete page-table walk.
FAQ
Why is it placed at the end of the sequence?
It is the trailing ordering boundary, ensuring prior SINVAL.VMA invalidations precede later implicit memory-management references; with H it also combines with HINVAL.*.