Does HINVAL.GVMA provide ordering by itself?
Not completely. It performs G-stage invalidation; SFENCE.W.INVAL and SFENCE.INVAL.IR provide ordering boundaries in the split-fence sequence.
HINVAL.GVMA
RISC-V HINVAL.GVMA Instruction Details
Instruction ManualR-typeSvinval/H G-stage translation invalidation: rs1 selects GPA>>2, rs2 selects VMID, and ordering is supplied by split fences.
Instruction Syntax
hinval.gvma rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
HSvinvalMemory Management
Instruction Behavior
HINVAL.GVMA is the Hypervisor + Svinval G-stage address-translation-cache invalidation instruction. It invalidates G-stage translation-cache entries matching rs1/rs2; nonzero rs1 contains the guest physical address shifted right by 2 bits (GPA>>2), and nonzero rs2 specifies a VMID. rs1=x0 selects all guest physical addresses, and rs2=x0 selects all VMIDs. It performs invalidation only; ordering is supplied by SFENCE.W.INVAL and SFENCE.INVAL.IR split fences.
HINVAL.GVMA Hypervisor Translation Decode Animation
Svinval/H G-stage invalidation: shows SYSTEM encoding, rs1/rs2 scope selection, and Svinval/H invalidation without modeling TLB or cache implementation.
rs1
rs2
hinval.gvma
,
G-stage Scope
rs2 selects VMID directly; nonzero rs1 holds GPA>>2.
31..25
24..20
19..15
14..12
11..7
6..0
0110011
funct7
01011
rs2/VMID
01010
rs1/GPA>>2
000
funct3
00000
rd=x0
1110011
SYSTEM
Hypervisor Translation State
instruction
0x66B50073
opcode
1110011 -> SYSTEM
funct7
0110011 -> HINVAL.GVMA
rs1
a0(x10) -> GPA>>2 0x0000000020000400
rs2
a1(x11) -> VMID 5
scope
a0(x10)=GPA>>2 0x0000000020000400 (GPA 0x0000000080001000); a1(x11)=VMID 5
invalidate
invalidate matching G-stage translation-cache entries
complete
selected G-stage translation-cache entries invalidated
This animation shows only the local-hart translation fence/invalidation semantics defined by the privileged architecture; it does not show OS shootdown protocols, TLB structures, cache flushes, page-walk latency, or platform interrupt mechanisms.
Quick Understanding & Search Notes
HINVAL.GVMA is the G-stage invalidation action inside a split-fence sequence: rs1 uses GPA>>2, rs2 uses VMID, and ordering is not supplied by this instruction alone.
funct7=0110011, funct3=000, rd=x0, opcode=1110011 identify HINVAL.GVMA.
HINVAL.GVMA follows HFENCE.GVMA scope selection: nonzero rs1 is GPA>>2, nonzero rs2 is VMID.
The typical split-fence relation is SFENCE.W.INVAL -> one or more HINVAL/SINVAL -> SFENCE.INVAL.IR.
Common Usage Scenarios
Svinval sequence
Understand this scenario with real code like «hinval.gvma a1, a2 # a1 = GPA >> 2; a2 = VMID».
G-stage invalidation
Understand this scenario with real code like «hinval.gvma a1, a2 # a1 = GPA >> 2; a2 = VMID».
Virtualization TLB shootdown
Understand this scenario with real code like «hinval.gvma a1, a2 # a1 = GPA >> 2; a2 = VMID».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Requires H plus Svinval; permissions/exceptions correspond to HFENCE.GVMA.
Nonzero rs1 contains GPA>>2, not a guest virtual address and not an unshifted GPA.
rs2 specifies VMID; rs2=x0 means all VMIDs.
It performs invalidation only and does not supply complete ordering; use SFENCE.W.INVAL and SFENCE.INVAL.IR for the split-fence sequence.
Do not read HINVAL.GVMA as a data-cache flush or concrete TLB-entry walk.
FAQ
Is HINVAL.GVMA rs1 the same as HINVAL.VVMA rs1?
No. Nonzero HINVAL.GVMA rs1 is GPA>>2; HINVAL.VVMA rs1 is guest virtual address.