Does HINVAL.GVMA provide ordering by itself?
Full ordering is not guaranteed alone. SFENCE.W.INVAL and SFENCE.INVAL.IR provide sequence ordering boundaries; implementations may use full HFENCE.
HINVAL.GVMA
RISC-V HINVAL.GVMA Instruction Details
Instruction ManualSYSTEM R-typeSvinval/H G-stage translation invalidation: rs1 selects GPA>>2, rs2 selects VMID, and ordering is supplied by split fences.
Instruction Syntax
hinval.gvma rs1, rs2
Operand Breakdown
rs1: supplies the GPA>>2; rs1=x0 selects all relevant guest physical addresses.
rs2: supplies the VMID; rs2=x0 selects all VMIDs.
A non-x0 HFENCE/HINVAL.GVMA rs1 holds GPA>>2; all XLEN bits belong to that encoded address value.
HSvinvalMemory Management
Instruction Behavior
HINVAL.GVMA is the Hypervisor + Svinval G-stage address-translation-cache invalidation instruction. It invalidates G-stage translation-cache entries matching rs1/rs2; rs1≠x0 contains the guest physical address shifted right by 2 bits (GPA>>2), and rs2≠x0 specifies a VMID. rs1=x0 selects all guest physical addresses, and rs2=x0 selects all VMIDs. It does not guarantee full ordering alone; SFENCE.W.INVAL and SFENCE.INVAL.IR supply the sequence ordering boundaries. Implementations may use the full matching HFENCE.
HINVAL.GVMA Hypervisor Translation Decode Animation
Svinval/H G-stage invalidation: shows SYSTEM encoding, rs1/rs2 scope selection, and Svinval/H invalidation without modeling TLB or cache implementation.
rs1
rs2
hinval.gvma
,
G-stage Scope
rs2 selects VMID directly; rs1≠x0 holds GPA>>2.
This example assumes H and Svinval, equal host/guest XLEN, valid addresses, and maximum implemented ID widths (RV32: ASID 9/VMID 7; RV64: ASID 16/VMID 14). High rs2 bits above the ID width are ignored; software should zero reserved high bits. Implementations may fence/invalidate a broader scope. The GPA input is shifted right by two into rs1; the register value is not shifted again.
31..25
24..20
19..15
14..12
11..7
6..0
0110011
funct7
01011
rs2/VMID
01010
rs1/GPA>>2
000
funct3
00000
rd=x0
1110011
SYSTEM
Hypervisor Translation State
instruction
0x66B50073
opcode
1110011 -> SYSTEM
funct7
0110011 -> HINVAL.GVMA
rs1
a0(x10) -> GPA>>2 0x0000000020000400
rs2
a1(x11)=0x0000000000000005 -> VMID 5
scope
a0(x10)=GPA>>2 0x0000000020000400 (GPA 0x0000000080001000); a1(x11)=0x0000000000000005 -> VMID 5
permission
HS; TVM=0
invalidate
Fence/invalidation effect not performed yet
complete
Fence/invalidation effect not performed yet
This animation shows only the local-hart translation fence/invalidation semantics defined by the privileged architecture; it does not show OS shootdown protocols, TLB structures, cache flushes, page-walk latency, or platform interrupt mechanisms.
Quick Understanding & Search Notes
HINVAL.GVMA is the G-stage invalidation action inside a split-fence sequence: rs1 uses GPA>>2, rs2 uses VMID, and full ordering is not guaranteed by this instruction alone.
funct7=0110011, funct3=000, rd=x0, opcode=1110011 identify HINVAL.GVMA.
HINVAL.GVMA follows HFENCE.GVMA scope selection: rs1≠x0 is GPA>>2, rs2≠x0 is VMID.
The typical split-fence relation is SFENCE.W.INVAL -> one or more HINVAL/SINVAL -> SFENCE.INVAL.IR.
Common Usage Scenarios
G-stage invalidation sequence
Understand this scenario with real code like «sfence.w.inval hinval.gvma a1, a2 # a1 = GPA >> 2; a2 = VMID sfence.inval.ir».
Pre-Use Checklist
Syntax Check
- Confirm the assembly has only rs1 and rs2: this SYSTEM R-type instruction has no rd writeback or immediate field.
- Confirm the rs1/rs2 scope: rs1=x0 selects all guest physical addresses, and rs2=x0 selects all VMIDs.
Semantic Check
- Confirm execution is in a permitted privilege state; when an illegal-instruction or virtual-instruction exception occurs, do not treat the invalidation effect as complete.
- Confirm a non-x0 rs1 already holds GPA>>2; do not shift the register value right again.
Pitfalls / Common Confusions
rs1≠x0 holds GPA>>2; do not shift the register value again.
Valid in M-mode; HS-mode requires mstatus.TVM=0. V=1 raises virtual-instruction; U-mode raises illegal-instruction.
Local-hart effect; implementations may cover a broader scope. This is not a generic data-cache flush.
For rs2≠x0, zero reserved high bits; bits above the implemented ID width are ignored.
Requires H and Svinval; SFENCE.W.INVAL → HINVAL → SFENCE.INVAL.IR in order supplies the matching HFENCE ordering boundaries.
FAQ
Is HINVAL.GVMA rs1 the same as HINVAL.VVMA rs1?
No. HINVAL.GVMA with rs1≠x0 is GPA>>2; HINVAL.VVMA rs1 is guest virtual address.