Is it a normal user-mode instruction?
No. These instructions are constrained by privilege level and extension support; user-mode legality must follow the privileged rules.
HINVAL.GVMA
RISC-V HINVAL.GVMA Instruction Details
Instruction ManualR-typeSvinval/H G-stage invalidation by GPA>>2 and VMID, with ordering supplied by split fences.
Instruction Syntax
hinval.gvma rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
HSvinvalMemory Management
Instruction Behavior
HINVAL.GVMA is the Hypervisor + Svinval G-stage address-translation-cache invalidation instruction. It invalidates G-stage translation-cache entries matching rs1/rs2; when rs1 is not x0, rs1 contains the guest physical address shifted right by 2 bits (GPA>>2), and when rs2 is not x0, rs2 specifies a VMID. rs1=x0 means all guest physical addresses, and rs2=x0 means all VMIDs. It performs invalidation only; ordering is supplied by SFENCE.W.INVAL and SFENCE.INVAL.IR.
Quick Understanding & Search Notes
HINVAL.GVMA is the Svinval/H G-stage address-translation invalidation; it performs invalidation only, while SFENCE.W.INVAL and SFENCE.INVAL.IR supply split-fence ordering.
HINVAL.GVMA follows HFENCE.GVMA address-selection semantics: nonzero rs1 denotes a guest physical address shifted right by 2 bits.
The instruction performs invalidation rather than a full fence; the split-fence sequence supplies ordering.
Common Usage Scenarios
Memory Management
Understand this scenario with real code like «hinval.gvma a1, a2 # a1 = GPA >> 2; a2 = VMID».
Virtualization
Understand this scenario with real code like «hinval.gvma a1, a2 # a1 = GPA >> 2; a2 = VMID».
TLB Shootdown
Understand this scenario with real code like «hinval.gvma a1, a2 # a1 = GPA >> 2; a2 = VMID».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Requires H plus Svinval, with permissions/exceptions corresponding to HFENCE.GVMA.
When rs1 is not x0 it contains GPA>>2, not a guest virtual address and not an unshifted GPA; rs2 specifies a VMID.
Execution in VS-mode or VU-mode raises a virtual-instruction exception.
Use with SFENCE.W.INVAL and SFENCE.INVAL.IR to obtain split-fence ordering.
FAQ
Does it replace ordinary memory fences?
No. Address translation, instruction fetch, and data-memory ordering use different fence/invalidation instructions.