Svinval address-translation invalidation instruction: uses rs1 virtual-address and rs2 address-space selectors to invalidate matching address-translation cache entries.
SINVAL.VMA is the supervisor address-translation invalidation instruction in the Svinval extension. It invalidates the address-translation cache entries that an SFENCE.VMA with the same rs1/rs2 operands would affect; rs1=x0 selects all virtual addresses, and rs2=x0 selects all address spaces, including global mappings. It performs invalidation and is not a generic data-cache flush; a split invalidation sequence is typically bracketed by SFENCE.W.INVAL before one or more SINVAL/HINVAL instructions and SFENCE.INVAL.IR after them.
Shows the SYSTEM encoding, VA/ASID scope selected by rs1/rs2, and address-translation invalidation within an Svinval sequence.
This animation shows only the local-hart invalidation/ordering relation defined by the privileged architecture; it does not simulate TLB structures, cache flushes, page-walk latency, IPIs, or OS shootdown protocols.
SINVAL.VMA is about scoped invalidation: rs1 selects the virtual-address scope and rs2 selects the address-space scope; the ordering boundaries are expressed by the companion SFENCE.W.INVAL and SFENCE.INVAL.IR instructions.
Understand this scenario with real code like «sinval.vma x0, x0 # invalidate all address spaces, including global mappings».
SINVAL.VMA uses the same rs1/rs2 scope selection as SFENCE.VMA for invalidating matching address-translation cache entries, while ordering in the split sequence is provided by SFENCE.W.INVAL and SFENCE.INVAL.IR.
No. As a SINVAL.VMA scope selector, rs2=x0 means all address spaces and includes global mappings.
No. The official semantics are address-translation cache invalidation and related ordering, not a generic data-cache flush.