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SINVAL.VMA

RISC-V SINVAL.VMA Instruction Details

Instruction ManualR-type

Svinval selective address-translation-cache invalidation by rs1 (VA) and rs2 (ASID); ordering is provided by SFENCE.W.INVAL/SFENCE.INVAL.IR.

Instruction Syntax

sinval.vma rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
PrivilegedSvinvalMemory Management
Related Search Terms
SINVAL.VMA instructionRISC-V SINVAL.VMAsinval.vma syntaxsinval.vma encodingsinval.vma Privileged/Svinvalsinval.vma privilegedsupervisor address-translation invalidation

Instruction Behavior

SINVAL.VMA invalidates the address-translation cache entries that an SFENCE.VMA with the same rs1/rs2 values would invalidate, but by itself it performs only invalidation; its ordering exists only with respect to SFENCE.VMA, SFENCE.W.INVAL, and SFENCE.INVAL.IR as specified. A typical batched sequence is SFENCE.W.INVAL -> multiple SINVAL.VMA/HINVAL.* instructions -> SFENCE.INVAL.IR. rs1=x0 means all virtual addresses, and rs2=x0 means all ASIDs.

Quick Understanding & Search Notes

SINVAL.VMA is a system-level instruction defined by the privileged architecture. This page covers architectural semantics only, not platform firmware policy.

The instruction affects address translation or invalidation ordering; it is not a generic data-cache flush.
Executing at an unsupported privilege level or without the required extension raises the specified exception.
RISC-V Privileged Architecture Manual, Supervisor-Level ISA

Common Usage Scenarios

Address & Pointer

Understand this scenario with real code like «sinval.vma x0, x0 # invalidate all TLB entries for all ASIDs».

Concurrency & Multi-core

Understand this scenario with real code like «sinval.vma x0, x0 # invalidate all TLB entries for all ASIDs».

Data Loading

Understand this scenario with real code like «sinval.vma x0, x0 # invalidate all TLB entries for all ASIDs».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is R-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

U-mode execution always raises illegal-instruction.
S-mode or HS-mode execution with mstatus.TVM=1 raises illegal-instruction.
VU-mode execution raises virtual-instruction; VS-mode execution raises virtual-instruction when hstatus.VTVM=1.
Ordering requires SFENCE.W.INVAL before and SFENCE.INVAL.IR after for the split-fence sequence.

FAQ

Is it a normal user-mode instruction?

No. These instructions are constrained by privilege level and extension support; user-mode legality must follow the privileged rules.

Does it replace ordinary memory fences?

No. Address translation, instruction fetch, and data-memory ordering use different fence/invalidation instructions.