Is it a normal user-mode instruction?
No. These instructions are constrained by privilege level and extension support; user-mode legality must follow the privileged rules.
HFENCE.VVMA
RISC-V HFENCE.VVMA Instruction Details
Instruction ManualR-typeHFENCE.VVMA is a VS-stage address-translation fence: order/invalidate local-hart translations for the current VMID by guest virtual address and ASID.
Instruction Syntax
hfence.vvma rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
HMemory Management
Instruction Behavior
HFENCE.VVMA is the Hypervisor extension VS-stage memory-management fence, similar in effect to temporarily entering VS-mode and executing SFENCE.VMA. It guarantees that prior stores already visible to the current hart are ordered before subsequent implicit reads for VS-stage address translation under the same VMID; if rs1 is not x0, it specifies a guest virtual address, and if rs2 is not x0, it specifies a guest ASID. The current VMID comes from hgatp.VMID, not rs2. rs1=x0 means all guest virtual addresses, and rs2=x0 means all ASIDs.
Quick Understanding & Search Notes
HFENCE.VVMA is the H-extension VS-stage address-translation fence, used to order updates to relevant two-stage translation structures with subsequent implicit translation on the local hart.
The instruction affects address translation or invalidation ordering; it is not a generic data-cache flush.
H-extension memory/fence instructions involve VS-stage and G-stage two-stage translation.
Common Usage Scenarios
Virtualization Memory Mgmt
Understand this scenario with real code like «hfence.vvma a1, a2».
Hypervisor Page-Table Sync
Understand this scenario with real code like «hfence.vvma a1, a2».
VM Switch
Understand this scenario with real code like «hfence.vvma a1, a2».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Local hart only; multicore systems need IPIs or another mechanism to make other harts execute corresponding fences.
rs1 is a guest virtual address; rs2 is a guest ASID, not a VMID.
HFENCE.VVMA is valid only in M-mode or HS-mode and is unaffected by mstatus.TVM or hstatus.VTVM.
FAQ
Does it replace ordinary memory fences?
No. Address translation, instruction fetch, and data-memory ordering use different fence/invalidation instructions.