RISC-V NOP Instruction Details
Instruction ManualI-type (HINT)No operation; a HINT instruction encoded as ADDI x0, x0, 0
Instruction Syntax
Instruction Encoding
NOP uses opcode 0010011 (0x13), funct3 000. The rs1 field selects the source register, the 12-bit immediate provides the second operand, and rd selects the destination.
Instruction Behavior
NOP is an assembler pseudo-instruction encoded as ADDI x0, x0, 0 (opcode=0010011, funct3=000, rd=x0, rs1=x0, imm=0). Since x0 is hardwired to zero and unwritable, this instruction changes no architectural state and produces no side effects. NOP occupies the HINT instruction space, used for pipeline padding, code alignment, or replacing disabled instructions. Other encodings besides ADDI x0,x0,0 also serve as NOPs (e.g., ADDI x0,x0,1), but the canonical NOP uses the all-zero immediate.
Common Usage Scenarios
Understand this scenario with real code like «nop # encoded as addi x0, x0, 0».
Understand this scenario with real code like «nop # encoded as addi x0, x0, 0».
Understand this scenario with real code like «nop # encoded as addi x0, x0, 0».
Pre-Use Checklist
- Confirm the current instruction format is I-type (HINT).
- Confirm the operand order matches the example.
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.