Does SHA512SUM0R use floating-point or vector registers?
No. These scalar crypto extension instructions use integer X registers.
SHA512SUM0R
RISC-V SHA512SUM0R Instruction Details
Instruction ManualR-typeSHA-512 Sum0 (RV32): two 32-bit source registers compute one half of the 64-bit Sum0 result
Instruction Syntax
sha512sum0r rd, rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
ZknhCrypto & Security
Instruction Encoding
31..25
funct7
24..20
rs2
19..15
rs1
14..12
funct3
11..7
rd
6..0
opcode
SHA512SUM0R uses opcode 0110011 (0x33), funct3 100, funct7 0101000. The rs1 and rs2 fields select the two source registers, and rd selects the destination register.
Format: R-type
opcode: 0110011 (0x33)
funct3: 100 (0x4)
funct7: 0101000 (0x28)
Instruction Behavior
sha512sum0r is an RV32 SHA-512 Sum transform instruction using two 32-bit source registers for the split 64-bit input; the full result is typically produced by executing it twice with reversed source-register order.
Quick Understanding & Search Notes
SHA512SUM0R is a Zknh scalar cryptography instruction for SHA-512 RV32 reversed-source transform. This page is checked against the official scalar crypto extension, avoiding confusion among round functions, key schedule steps, and operand sources.
sha512sum0r is a two-source RV32 instruction for a SHA-512 Sum transform; the full 64-bit result is computed by executing it twice with reversed source-register order.
Scalar crypto instructions use integer X registers, and the official spec requires the relevant crypto instructions to be implemented with data-independent execution latency.
RV32 SHA-512 split forms need the official h/l or reversed-source sequence to assemble the full 64-bit result.
Common Usage Scenarios
Crypto & Security
Understand this scenario with real code like «sha512sum0r t0, a0, a1 ; compute one RV32 half, repeat with sources reversed».
Hash Algorithms
Understand this scenario with real code like «sha512sum0r t0, a0, a1 ; compute one RV32 half, repeat with sources reversed».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
RV32 only; sha512sum0r produces only one half of the split 64-bit Σ0 result.
The full result requires the official sequence that executes again with rs1/rs2 reversed; it is not a single-register alias of RV64 sha512sum0.
FAQ
Is SHA512SUM0R a complete algorithm implementation?
No. It is a low-level step from AES, SHA, SM3, or SM4; software still combines instructions with the algorithm schedule, round constants, or round keys.