Does SHA512SUM1R use floating-point or vector registers?
No. These scalar crypto extension instructions use integer X registers.
SHA512SUM1R
RISC-V SHA512SUM1R Instruction Details
Instruction ManualR-typeSHA-512 Sum1: two RV32 source words produce one 32-bit result word
Instruction Syntax
sha512sum1r rd, rs1, rs2
Syntax is sha512sum1r rd, rs1, rs2; operands select integer x0–x31 or ABI names, with no assembly immediate.
32-bit OP: funct7=0101001, funct3=000, opcode=0110011.
RV32 Zknh only (also in Zkn/Zk); each instruction computes one 32-bit result word. Preserve the original inputs and reverse source order for the second instruction of the full Sum transform.
An x0 source is zero and writes to x0 are discarded; overlap reads values before writeback and equal sources share one value. Execution latency must be data-independent.
ZknhCrypto & Security
Instruction Behavior
sha512sum1r is defined only for RV32. It applies the official formula to the 32-bit X(rs1) and X(rs2) values to compute one SHA2-512 Sum1 result word; the documented two-instruction sequence reverses the source-register order for its second instruction.
SHA512SUM1R Decode And Execute Animation
Applies the official RV32 formula for one SHA-512 Sum result word.
rd
rs1
rs2
sha512sum1r
,
,
Execution Context
XLEN is fixed at 32. This instruction reads rs1 and rs2 exactly as shown; the official two-instruction sequence reverses the source-register order for its second instruction. Initially rd shares an overlapping source value, otherwise it starts at 0. An x0 source must be 0; identical sources must share one value.
fixed
source
source
fixed
destination
OP
31..25
0101001
24..20
rs2=x12
19..15
rs1=x11
14..12
000
11..7
rd=x10
6..0
0110011
Execution Data Path
X(rs1)[31:0]
0x89ABCDEF
X(rs2)[31:0]
0x01234567
rs1 << 23
0xF7800000
rs1 >> 14
0x000226AF
rs1 >> 18
0x0000226A
rs2 >> 9
0x000091A2
rs2 << 18
0x159C0000
rs2 << 14
0xD159C000
result
0x33475567
Architectural Result
a0(x10) = 0x00000000
This animation shows only official ISA fields and architectural state; it does not model a complete hash algorithm or microarchitecture.
Quick Understanding & Search Notes
sha512sum1r computes SHA-512 Sum1 as one RV32 result word; reverse the source registers for the other word.
All operands are integer X registers; this instruction must have data-independent execution latency.
Common Usage Scenarios
Crypto & Security
RV32 Zknh, a0=1 and a1=0; preserve both sources and reverse their order in the second instruction. t0=0x00800000, t1=0x00044000.
Hash Algorithms
RV32 Zknh, a0=1 and a1=0; preserve both sources and reverse their order in the second instruction. t0=0x00800000, t1=0x00044000.
Pre-Use Checklist
Syntax Check
- Syntax is sha512sum1r rd, rs1, rs2; operands select integer x0–x31 or ABI names, with no assembly immediate.
- 32-bit OP: funct7=0101001, funct3=000, opcode=0110011.
Semantic Check
- RV32 Zknh only (also in Zkn/Zk); each instruction computes one 32-bit result word. Preserve the original inputs and reverse source order for the second instruction of the full Sum transform.
- An x0 source is zero and writes to x0 are discarded; overlap reads values before writeback and equal sources share one value. Execution latency must be data-independent.
Pitfalls / Common Confusions
RV32 only; sha512sum1r produces only one half of the split 64-bit Σ1 result.
The full result requires the official sequence that executes again with rs1/rs2 reversed; it is not a single-register alias of RV64 sha512sum1.
FAQ
Is SHA512SUM1R a complete algorithm implementation?
No. It computes one RV32 result word of SHA2-512 Sum1; the manual's second instruction reverses the source-register order.