Does SHA512SUM1R use floating-point or vector registers?
No. These scalar crypto extension instructions use integer X registers.
SHA512SUM1R
RISC-V SHA512SUM1R Instruction Details
Instruction ManualR-typeSHA-512 Sum1 (RV32): two 32-bit source registers compute one half of the 64-bit Sum1 result
Instruction Syntax
sha512sum1r rd, rs1, rs2
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
ZknhCrypto & Security
Instruction Behavior
sha512sum1r is defined only for RV32. It applies the official formula to the 32-bit X(rs1) and X(rs2) values to compute one SHA2-512 Sum1 result word; the documented two-instruction sequence reverses the source-register order for its second instruction.
SHA512SUM1R Decode And Execute Animation
Applies the official RV32 formula for one SHA-512 Sum result word.
rd
rs1
rs2
sha512sum1r
,
,
Execution Context
XLEN is fixed at 32. This instruction reads rs1 and rs2 exactly as shown; the official two-instruction sequence reverses the source-register order for its second instruction.
fixed
source
source
fixed
destination
OP
31..25
0101001
24..20
rs2=x12
19..15
rs1=x11
14..12
000
11..7
rd=x10
6..0
0110011
Execution Data Path
X(rs1)[31:0]
0x89ABCDEF
X(rs2)[31:0]
0x01234567
rs1 << 23
0xF7800000
rs1 >> 14
0x000226AF
rs1 >> 18
0x0000226A
rs2 >> 9
0x000091A2
rs2 << 18
0x159C0000
rs2 << 14
0xD159C000
result
0x33475567
Architectural Result
a0(x10) = 0x33475567
This animation shows only official ISA fields and architectural state; it does not model a complete hash algorithm or microarchitecture.
Quick Understanding & Search Notes
SHA512SUM1R is a Zknh scalar cryptography instruction for SHA-512 RV32 reversed-source transform. This page is checked against the official scalar crypto extension, avoiding confusion among round functions, key schedule steps, and operand sources.
sha512sum1r is a two-source RV32 instruction for a SHA-512 Sum transform; the full 64-bit result is computed by executing it twice with reversed source-register order.
Scalar crypto instructions use integer X registers, and the official spec requires the relevant crypto instructions to be implemented with data-independent execution latency.
RV32 SHA-512 split forms need the official h/l or reversed-source sequence to assemble the full 64-bit result.
Common Usage Scenarios
Crypto & Security
Understand this scenario with real code like «sha512sum1r t0, a0, a1 ; compute one RV32 half, repeat with sources reversed».
Hash Algorithms
Understand this scenario with real code like «sha512sum1r t0, a0, a1 ; compute one RV32 half, repeat with sources reversed».
Pre-Use Checklist
Syntax Check
- Verify rd, rs1, rs2 (and rs3) are valid GPRs.
- Confirm funct3 and funct7 encoding is correct.
Semantic Check
- Check if the result affects subsequent branches or address calculations.
- Ensure the rd register is not overwritten by another instruction.
Pitfalls / Common Confusions
RV32 only; sha512sum1r produces only one half of the split 64-bit Σ1 result.
The full result requires the official sequence that executes again with rs1/rs2 reversed; it is not a single-register alias of RV64 sha512sum1.
FAQ
Is SHA512SUM1R a complete algorithm implementation?
No. It computes one RV32 result word of SHA2-512 Sum1; the manual's second instruction reverses the source-register order.