Does SHA512SUM1 use floating-point or vector registers?
No. These scalar crypto extension instructions use integer X registers.
SHA512SUM1
RISC-V SHA512SUM1 Instruction Details
Instruction ManualI-typeSHA-512 Σ1 function (uppercase, RV64): ROTR(rs1,14) ^ ROTR(rs1,18) ^ ROTR(rs1,41)
Instruction Syntax
sha512sum1 rd, rs1
Syntax is sha512sum1 rd, rs1; operands select integer x0–x31 or ABI names, with no assembly immediate.
32-bit OP-IMM: bits31..20=000100000101, funct3=001, opcode=0010011; the selector is a fixed encoding field.
RV64 Zknh only (also in Zkn/Zk); apply this page's fixed right rotations and XOR to the complete 64-bit source.
An x0 source is zero and writes to x0 are discarded; overlap reads values before writeback and equal sources share one value. Execution latency must be data-independent.
ZknhCrypto & Security
Instruction Behavior
sha512sum1 is defined only for RV64. It computes the SHA2-512 Sum1 transform, ROTR64(X(rs1), 14) ^ ROTR64(X(rs1), 18) ^ ROTR64(X(rs1), 41), and writes the 64-bit result to rd. sha512sum1r is the RV32 split form.
SHA512SUM1 Decode And Execute Animation
Bounded teaching inputs execute the official SHA-512 fixed-width bit operations; this does not model a complete algorithm or microarchitecture.
rd
rs1
sha512sum1
,
Initially rd shares the source value when rd=rs1; otherwise the demo starts rd at 0. An rs1=x0 source always reads 0. SHA512SUM1 is defined only for RV64 and operates on the complete 64-bit X(rs1).
fixed selector
source
fixed
destination
OP-IMM
31..20
000100000101
19..15
rs1=x11
14..12
001
11..7
rd=x10
6..0
0010011
Execution Data Path
inb
0x0123456789ABCDEF
ror64(inb, 14)
0x37BC048D159E26AF
ror64(inb, 18)
0xF37BC048D159E26A
ror64(inb, 41)
0xB3C4D5E6F78091A2
result
0x7703112333475567
Architectural Result
a0(x10) = 0x0000000000000000
This animation shows only official ISA fields and architectural state; it does not model a complete hash algorithm, pipeline, cache, or timing implementation.
Quick Understanding & Search Notes
sha512sum1 computes SHA-512 Sum1 on a complete 64-bit source and result.
All operands are integer X registers; this instruction must have data-independent execution latency.
Common Usage Scenarios
Crypto & Security
RV64 Zknh, a1=1: the page's formula gives a0=0x0004400000800000.
Hash Algorithms
RV64 Zknh, a1=1: the page's formula gives a0=0x0004400000800000.
Pre-Use Checklist
Syntax Check
- Syntax is sha512sum1 rd, rs1; operands select integer x0–x31 or ABI names, with no assembly immediate.
- 32-bit OP-IMM: bits31..20=000100000101, funct3=001, opcode=0010011; the selector is a fixed encoding field.
Semantic Check
- RV64 Zknh only (also in Zkn/Zk); apply this page's fixed right rotations and XOR to the complete 64-bit source.
- An x0 source is zero and writes to x0 are discarded; overlap reads values before writeback and equal sources share one value. Execution latency must be data-independent.
Pitfalls / Common Confusions
RV64 only; RV32 uses the two-instruction sha512sum1r sequence.
Bits 31..20 are a fixed selector, with no assembly immediate.
FAQ
Is SHA512SUM1 a complete algorithm implementation?
No. It implements one SHA2-512 Sum1 transform defined by the manual.