Does SHA512SUM0 use floating-point or vector registers?
No. These scalar crypto extension instructions use integer X registers.
SHA-512 Σ0 function (uppercase, RV64): ROTR(rs1,28) ^ ROTR(rs1,34) ^ ROTR(rs1,39)
sha512sum0 implements SHA-512 compression Σ0 (uppercase) (RV64 only): Σ0(x) = ROTR(x, 28) ^ ROTR(x, 34) ^ ROTR(x, 39). Reads 64-bit rs1, computes Σ0, writes to rd. For SHA-512 compression A-register update. On RV32, sha512sum0r provides the equivalent.
SHA512SUM0 is a Zknh scalar cryptography instruction for SHA-512 RV64 transform. This page is checked against the official scalar crypto extension, avoiding confusion among round functions, key schedule steps, and operand sources.
Understand this scenario with real code like «sha512sum0 a0, a1».
Understand this scenario with real code like «sha512sum0 a0, a1».
No. These scalar crypto extension instructions use integer X registers.
No. It is a low-level step from AES, SHA, SM3, or SM4; software still combines instructions with the algorithm schedule, round constants, or round keys.