How is VASUBU.VX different from ordinary VSUB?
VASUBU.VX is fixed-point averaging subtract and rounds the one-bit shifted result with vxrm; ordinary integer subtract does not use vxrm.
VASUBU.VX
RISC-V VASUBU.VX Instruction Details
Instruction ManualV-typevector-scalar unsigned averaging subtract: active elements read vs2 and x[rs1], round according to vxrm, and write the SEW-width vd result.
Instruction Syntax
vasubu.vx vd, vs2, rs1[, v0.t]
Operand Breakdown
vd and vs2 are SEW-wide vector groups; same-EEW source/destination overlap is allowed, and equal sources read equal initial values.
rs1 is an integer scalar: use low SEW bits for XLEN>SEW, sign-extend for XLEN<SEW, including unsigned VASUBU; x0 supplies zero.
Interpret signedness as specified, form the infinite-precision difference, shift right one bit and round using vxrm, then truncate to SEW; overflow wraps, without saturation or a vxsat update.
Require V and support for the selected vtype. vm=0 uses v0.t; vm=1 is unmasked. Only active body elements compute, with inactive/tail values governed by vma/vta. Masked vd cannot overlap v0, which cannot also supply different-EEW data.
VVector OperationsFixed-Point Arithmetic
Instruction Behavior
vasubu.vx is an RVV fixed-point averaging subtract instruction. It operates on active elements within vl, uses the vxrm rnu/rne/rdn/rod rounding mode, and is controlled by vm/v0.t masking.
VASUBU.VX Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VASUBU uses the infinite-precision difference for averaging subtract, rounds with vxrm, and writes the SEW-width vd result; final overflow wraps as specified.
Instruction input
vasubu.vx
Require valid vtype, enabled VS, and supported SEW; VL=0 updates nothing, including tails. Steps are teaching stages, not processor cycles.
Execution Context
The teaching model fixes LMUL=m1 and vstart=0 and shows only body elements in the selected VL. It fixes VLEN=4096, VLMAX=4096/16=256, and assumes support for the selected SEW; equal vector sources require equal elements. In ordinary masked forms, inactive and tail elements follow vtype.vma/vta and the result row does not invent a definite value; VADC/VMADC/VSBC/VMSBC execute every body element, with v0 bits used only as carry/borrow-in.
OP-V encodingvasubu.vx
funct6
001010
vm
0
vs2
01000
rs1
01011
funct3
110
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x0021
0x007f
0x0080
0x00f1
0x0012
0x00fe
0x0021
0x007f
avg-
avg-
avg-
avg-
avg-
avg-
avg-
avg-
x11
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vasubu.vx uses OP-V encoding. The animation places fixed fields, register fields, vm, and the rs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer unsigned averaging subtraction, vxrm fixed-point rounding, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VASUBU.VX is RVV fixed-point averaging subtract. Source elements are interpreted as unsigned values, the result is rounded by vxrm and written to the SEW-width vd element; it does not set floating-point exception flags and is not a saturating instruction.
vasubu.vx vd, vs2, rs1, vm uses OP-V encoding; the .vx form is selected by funct3 and funct6 selects VASUBU.
Averaging subtract rounds the one-bit shift of the infinite-precision difference; the specification states that VASUB/VASUBU ignore overflow and wrap.
The rounding mode comes from the fixed-point rounding mode CSR vxrm: rnu, rne, rdn, or rod.
Only active body elements within vl are processed; vm=0 uses v0.t, and tail or masked-off destination elements follow vtype policies.
Vector Execution Context
vd and vs2 are SEW-wide vector groups; same-EEW source/destination overlap is allowed, and equal sources read equal initial values.
rs1 is an integer scalar: use low SEW bits for XLEN>SEW, sign-extend for XLEN<SEW, including unsigned VASUBU; x0 supplies zero.
Interpret signedness as specified, form the infinite-precision difference, shift right one bit and round using vxrm, then truncate to SEW; overflow wraps, without saturation or a vxsat update.
Require V and support for the selected vtype. vm=0 uses v0.t; vm=1 is unmasked. Only active body elements compute, with inactive/tail values governed by vma/vta. Masked vd cannot overlap v0, which cannot also supply different-EEW data.
Common Usage Scenarios
Fixed-point averaging
Assume V with supported e16,m1 and VLMAX≥4, a0=4, vxrm=rne, and v0 bits 1010 in lane order 0..3. Each vs2 element is 1 and the second-source elements are 2. Active lanes 0 and 2 produce 0: rne rounds -0.5 to even zero; inactive and tail elements follow ma/ta.
Vector data processing
Assume V with supported e16,m1 and VLMAX≥4, a0=4, vxrm=rne, and v0 bits 1010 in lane order 0..3. Each vs2 element is 1 and the second-source elements are 2. Active lanes 0 and 2 produce 0: rne rounds -0.5 to even zero; inactive and tail elements follow ma/ta.
RVV masked execution
Assume V with supported e16,m1 and VLMAX≥4, a0=4, vxrm=rne, and v0 bits 1010 in lane order 0..3. Each vs2 element is 1 and the second-source elements are 2. Active lanes 0 and 2 produce 0: rne rounds -0.5 to even zero; inactive and tail elements follow ma/ta.
Pre-Use Checklist
Syntax Check
- vd and vs2 are SEW-wide vector groups; same-EEW source/destination overlap is allowed, and equal sources read equal initial values.
- rs1 is an integer scalar: use low SEW bits for XLEN>SEW, sign-extend for XLEN<SEW, including unsigned VASUBU; x0 supplies zero.
Semantic Check
- Interpret signedness as specified, form the infinite-precision difference, shift right one bit and round using vxrm, then truncate to SEW; overflow wraps, without saturation or a vxsat update.
- Require V and support for the selected vtype. vm=0 uses v0.t; vm=1 is unmasked. Only active body elements compute, with inactive/tail values governed by vma/vta. Masked vd cannot overlap v0, which cannot also supply different-EEW data.
Pitfalls / Common Confusions
Rounding is controlled by vxrm; this is not a fixed add-one-then-shift operation.
VASUB/VASUBU compute the pre-rounding difference in infinite precision; if the averaging-subtract result overflows, the final SEW-width result wraps.
When vm=0, v0.t controls active elements; masked-off and tail elements follow the current vtype policies.
FAQ
Does VASUBU.VX set vxsat?
No. This instruction uses vxrm rounding but is not a saturating instruction; use saturating fixed-point instructions such as VSADD/VSSUB when saturation is required.