Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VFMERGE.VFM
RISC-V VFMERGE.VFM Instruction Details
Instruction ManualR-typeMerge vs2[i] with f[rs1] under v0: mask 1 selects f[rs1], mask 0 selects vs2[i].
Instruction Syntax
vfmerge.vfm vd, vs2, rs1, v0
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VZvfhVector OperationsFloating-Point
Instruction Behavior
VFMERGE.VFM merges a floating-point scalar with vector elements. For each element, v0.mask[i]=1 selects f[rs1] for vd[i], while v0.mask[i]=0 selects vs2[i]; v0 is the selection mask rather than a normal execution mask.
Quick Understanding & Search Notes
VFMERGE.VFM is conditional selection, not arithmetic. The common mistake is reversing the selection direction: mask bit 1 selects the FP scalar, and mask bit 0 selects the vs2 element.
The instruction uses v0 as the merge-selection mask.
The operation applies only to active elements within vl; inactive and tail elements follow the current vma/vta policy.
Except for dedicated mask forms, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
Floating-point operations follow the vector FP rules: normal FP operations use frm rounding and set FP exception flags; fixed-point vxrm does not control them.
Vector Execution Context
When reading VFMERGE.VFM, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Conditional Assignment
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfmerge.vfm v1, v2, ft0, v0 # v0[i] ? ft0 : v2[i]».
Ternary Operator
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfmerge.vfm v1, v2, ft0, v0 # v0[i] ? ft0 : v2[i]».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Mask is always v0; no other mask register allowed. No vm bit — always masked operation.
vfmerge.vfm is float version of vmerge.vxm. Scalar from f register, not x register.
Vector FP32/FP64 operations require matching scalar F/D support; FP16 operation is not implied by V alone.
FAQ
Which operand is selected when the mask bit is 1?
It selects floating-point scalar f[rs1]; mask bit 0 selects vs2[i].