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VFMERGE.VFM

RISC-V VFMERGE.VFM Instruction Details

Instruction ManualV-type

Merge vs2[i] with f[rs1] under v0: mask 1 selects f[rs1], mask 0 selects vs2[i].

Instruction Syntax

vfmerge.vfm vd, vs2, rs1, v0
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector OperationsFloating-Point
Related Search Terms
VFMERGE.VFM instructionRISC-V VFMERGE.VFMvfmerge.vfm syntaxvfmerge.vfm RVVFP mergev0 select

Instruction Behavior

VFMERGE.VFM merges a floating-point scalar with vector elements. For each element, v0.mask[i]=1 selects f[rs1] for vd[i], while v0.mask[i]=0 selects vs2[i]; v0 is the selection mask rather than a normal execution mask.

VFMERGE.VFM Decode And Execute Animation

Decode OP-V and merge every body element: fixed vm=0 makes each v0 bit select f[rs1] or vs2[i], without masking execution.

Instruction input
vfmerge.vfm
vm0fixed 0: v0 selects operands; it does not mask execution
Execution context
LMULm1fixed register-group multiplier
VLEN4096fixed vector-register length (bits)
VLMAX128maximum element count at m1
vstart0prestart elements are outside this animation
frmRNEfinite teaching context fixed at RNE; the architectural instruction uses dynamic frm
FP stateFS enabledFS=Off raises illegal instruction; this animation fixes the architectural state to FS enabled
vta / vmata, mamerge writes every body element; only tails use vta
opcode1010111OP-V major opcode
Encoding fields
0x5c855257
31..26
25
24..20
19..15
14..12
11..7
6..0
010111
funct6
0
vm
01000
vs2
01010
rs1
101
funct3
00100
vd
1010111
OP-V
Execution data path

lane 0: v0[1] ? 1.5 : 1 -> 0x3fc00000 (1.5)

This lane follows the current-step highlight; the remaining lane results appear below.

Step 1 / 15
Read OP-V encoding fields

V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.

Lane results
Long vectors scroll inside this module without page overflow.
i=0active
v0[1] ? 1.5 : 1
0x3fc00000 (1.5)
i=1active
v0[1] ? 1.5 : 1.5
0x3fc00000 (1.5)
i=2active
v0[0] ? 1.5 : 2
0x40000000 (2)
i=3active
v0[1] ? 1.5 : 2.5
0x3fc00000 (1.5)
i=4active
v0[1] ? 1.5 : -3
0x3fc00000 (1.5)
i=5active
v0[1] ? 1.5 : 3.5
0x3fc00000 (1.5)
i=6active
v0[0] ? 1.5 : 4
0x40800000 (4)
i=7active
v0[1] ? 1.5 : 4.5
0x3fc00000 (1.5)
SEW=32 / binary32 demo copies the selected IEEE bit pattern: v0[i]=1 copies f[rs1], and v0[i]=0 copies vs2[i]. Fixed vm=0 is not an execution mask; every body element is written, prestart remains unchanged, and tails follow vta. When FLEN exceeds SEW, scalar f[rs1] must be validly NaN-boxed or is architecturally treated as canonical NaN.

Quick Understanding & Search Notes

VFMERGE.VFM is conditional selection, not arithmetic. The common mistake is reversing the selection direction: mask bit 1 selects the FP scalar, and mask bit 0 selects the vs2 element.

The instruction uses v0 as the merge-selection mask.
It operates on every body element from vstart through vl-1; v0 bits only select sources, so this mask creates no inactive elements, while tails follow vta.
The encoded vm bit is fixed to 0: v0.mask[i]=1 selects f[rs1], and 0 selects vs2[i].
When FLEN exceeds SEW, the scalar f[rs1] used by the vector-scalar form must be validly NaN-boxed; otherwise the scalar operand is treated as canonical NaN.
RISC-V Unprivileged ISA Manual: V Standard Extension for Vector Operations

Vector Execution Context

When reading VFMERGE.VFM, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

Conditional Assignment

Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfmerge.vfm v1, v2, ft0, v0 # v0[i] ? ft0 : v2[i]».

Ternary Operator

Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfmerge.vfm v1, v2, ft0, v0 # v0[i] ? ft0 : v2[i]».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is V-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

The selection mask is always v0 and the encoded vm bit is fixed to 0; it is not an optional ordinary execution mask.
VFMERGE.VFM is the floating-point version of vmerge.vxm. Its scalar operand comes from an f register, not an x register.
Vector FP32/FP64 operations require matching scalar F/D support; FP16 operation is not implied by V alone.

FAQ

Which operand is selected when the mask bit is 1?

It selects floating-point scalar f[rs1]; mask bit 0 selects vs2[i].