Which operand is selected when the mask bit is 1?
It selects floating-point scalar f[rs1]; mask bit 0 selects vs2[i].
VFMERGE.VFM
RISC-V VFMERGE.VFM Instruction Details
Instruction ManualV-typeMerge vs2[i] with f[rs1] under v0: mask 1 selects f[rs1], mask 0 selects vs2[i].
Instruction Syntax
vfmerge.vfm vd, vs2, rs1, v0
Operand Breakdown
vd and vs2 are SEW-wide vector groups; same-EEW destination/source overlap is legal and equal sources read equal initial values. There is no immediate operand.
rs1 selects FP f0–f31 or an ABI name; when FLEN>SEW an invalid NaN box is read as canonical NaN.
v0 is a required selection source with fixed vm=0: v0[i]=1 selects f[rs1], 0 selects vs2[i], and all body elements are written.
Require V, supported vtype and FP widths, and enabled VS/FS; V supports FP32/FP64 and depends on F/D. With H and virtualization V=1, vsstatus.VS/FS must also be enabled. Invalid frm use is reserved even if no rounding occurs or vl=0.
Prestart is unchanged; vl=0 or vstart≥vl leaves every destination element, including tails, unchanged. Otherwise inactive/tail elements follow vma/vta, with no guaranteed zeroing or preservation.
With vm=0, vd cannot overlap v0; v0 cannot supply both an EEW=1 selection/mask source and SEW data. Successful execution resets vstart to zero.
VVector OperationsFloating-Point
Instruction Behavior
VFMERGE.VFM merges a floating-point scalar with vector elements. For each body element from vstart through vl-1, v0.mask[i]=1 selects f[rs1] for vd[i], while v0.mask[i]=0 selects vs2[i]; v0 is the selection mask rather than a normal execution mask.
VFMERGE.VFM Decode And Execute Animation
Decode OP-V and merge every body element: fixed vm=0 makes each v0 bit select f[rs1] or vs2[i], without masking execution.
Instruction input
vfmerge.vfm
vmfixed 0: v0 selects operands; it does not mask execution
Execution context
LMULfixed register-group multiplier
VLENfixed vector-register length (bits)
VLMAXmaximum element count at m1
vstartprestart elements are outside this animation
frmnot rounded by frm; the architectural instruction still requires valid frm
FP stateFS=Off raises illegal instruction; this animation fixes the architectural state to FS enabled
vta / vmamerge writes every body element; only tails use vta
opcodeOP-V major opcode
Encoding fields
0x5c855257
31..26
25
24..20
19..15
14..12
11..7
6..0
010111
funct6
0
vm
01000
vs2
01010
rs1
101
funct3
00100
vd
1010111
OP-V
Execution data path
lane 0: v0[i]=1: 1.5 -> 0x3fc00000 (1.5)
This lane follows the current-step highlight; the remaining lane results appear below.
Step 1 / 15
Read OP-V encoding fields
V-extension FP instructions use the OP-V major opcode, with funct6, source registers, vm, funct3, vd, and opcode fields.
Lane results
Long vectors scroll inside this module without page overflow.
i=0active
v0[i]=1: 1.5
0x3fc00000 (1.5)
i=1active
v0[i]=1: 1.5
0x3fc00000 (1.5)
i=2active
v0[i]=0: 2
0x40000000 (2)
i=3active
v0[i]=1: 1.5
0x3fc00000 (1.5)
i=4active
v0[i]=1: 1.5
0x3fc00000 (1.5)
i=5active
v0[i]=1: 1.5
0x3fc00000 (1.5)
i=6active
v0[i]=0: 4
0x40800000 (4)
i=7active
v0[i]=1: 1.5
0x3fc00000 (1.5)
SEW=32 / binary32 demo copies the selected IEEE bit pattern: v0[i]=1 copies f[rs1], and v0[i]=0 copies vs2[i]. Fixed vm=0 is not an execution mask; every body element is written, prestart remains unchanged, and tails follow vta. When FLEN exceeds SEW, scalar f[rs1] must be validly NaN-boxed or is architecturally treated as canonical NaN.
This teaching context fixes VS/FS enabled, valid vtype, frm=RNE, and FLEN=64; a SEW=32 scalar input represents the low 32 bits of a valid NaN box. Equal sources require equal bits. Same-width destination/source overlap is legal; ta/ma gives no definite inactive or tail value. At VL=0 no destination elements, including tails, are updated.
Quick Understanding & Search Notes
VFMERGE.VFM is conditional selection, not arithmetic. The common mistake is reversing the selection direction: mask bit 1 selects the FP scalar, and mask bit 0 selects the vs2 element.
The instruction uses v0 as the merge-selection mask.
It operates on every body element from vstart through vl-1; v0 bits only select sources, so this mask creates no inactive elements, while tails follow vta.
The encoded vm bit is fixed to 0: v0.mask[i]=1 selects f[rs1], and 0 selects vs2[i].
When FLEN exceeds SEW, the scalar f[rs1] used by the vector-scalar form must be validly NaN-boxed; otherwise the scalar operand is treated as canonical NaN.
This page covers V 1.0: V depends on F/D and supports FP SEW=32/64; VS/FS must be enabled and vtype valid. An invalid frm is reserved even though this operation does not round by frm. The scalar comes from an f register; when FLEN>SEW, an invalid NaN box is read as canonical NaN.
The 32-bit OP-V encoding uses funct6=010111, funct3=101, and vm=0. vd cannot overlap v0; vs2 cannot read v0 both as SEW data and as an EEW=1 selection source.
Vector Execution Context
vd and vs2 are SEW-wide vector groups; same-EEW destination/source overlap is legal and equal sources read equal initial values. There is no immediate operand.
rs1 selects FP f0–f31 or an ABI name; when FLEN>SEW an invalid NaN box is read as canonical NaN.
v0 is a required selection source with fixed vm=0: v0[i]=1 selects f[rs1], 0 selects vs2[i], and all body elements are written.
Require V, supported vtype and FP widths, and enabled VS/FS; V supports FP32/FP64 and depends on F/D. With H and virtualization V=1, vsstatus.VS/FS must also be enabled. Invalid frm use is reserved even if no rounding occurs or vl=0.
Prestart is unchanged; vl=0 or vstart≥vl leaves every destination element, including tails, unchanged. Otherwise inactive/tail elements follow vma/vta, with no guaranteed zeroing or preservation.
With vm=0, vd cannot overlap v0; v0 cannot supply both an EEW=1 selection/mask source and SEW data. Successful execution resets vstart to zero.
Common Usage Scenarios
Conditional Assignment
Assume V/VS/FS enabled, valid frm, supported e32,m1, VLMAX≥4, x10=4, vstart=0, and v2=[1,-2,3,+0]; scalars are validly NaN-boxed. v0=[1,0,1,0], f0=1.5 → v1=[1.5,-2,1.5,+0]. Min/max examples omit v0.t, so all four body elements execute; merge uses v0 only for selection. Tails follow ta without assumed zeroing.
Ternary Operator
Assume V/VS/FS enabled, valid frm, supported e32,m1, VLMAX≥4, x10=4, vstart=0, and v2=[1,-2,3,+0]; scalars are validly NaN-boxed. v0=[1,0,1,0], f0=1.5 → v1=[1.5,-2,1.5,+0]. Min/max examples omit v0.t, so all four body elements execute; merge uses v0 only for selection. Tails follow ta without assumed zeroing.
Pre-Use Checklist
Syntax Check
- vd and vs2 are SEW-wide vector groups; same-EEW destination/source overlap is legal and equal sources read equal initial values. There is no immediate operand.
- rs1 selects FP f0–f31 or an ABI name; when FLEN>SEW an invalid NaN box is read as canonical NaN.
Semantic Check
- v0 is a required selection source with fixed vm=0: v0[i]=1 selects f[rs1], 0 selects vs2[i], and all body elements are written.
- Require V, supported vtype and FP widths, and enabled VS/FS; V supports FP32/FP64 and depends on F/D. With H and virtualization V=1, vsstatus.VS/FS must also be enabled. Invalid frm use is reserved even if no rounding occurs or vl=0.
- Prestart is unchanged; vl=0 or vstart≥vl leaves every destination element, including tails, unchanged. Otherwise inactive/tail elements follow vma/vta, with no guaranteed zeroing or preservation.
- With vm=0, vd cannot overlap v0; v0 cannot supply both an EEW=1 selection/mask source and SEW data. Successful execution resets vstart to zero.
Pitfalls / Common Confusions
The selection mask is always v0 and the encoded vm bit is fixed to 0; it is not an optional ordinary execution mask.
VFMERGE.VFM is the floating-point version of vmerge.vxm. Its scalar operand comes from an f register, not an x register.
V depends on F and D and supports FP32/FP64; V alone does not provide FP16 operations.