Which operand is selected when the mask bit is 1?
It selects floating-point scalar f[rs1]; mask bit 0 selects vs2[i].
VFMERGE.VFM
RISC-V VFMERGE.VFM Instruction Details
Instruction ManualR-typeMerge vs2[i] with f[rs1] under v0: mask 1 selects f[rs1], mask 0 selects vs2[i].
Instruction Syntax
vfmerge.vfm vd, vs2, rs1, v0
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
VZvfhVector OperationsFloating-Point
Instruction Behavior
VFMERGE.VFM merges a floating-point scalar with vector elements. For each element, v0.mask[i]=1 selects f[rs1] for vd[i], while v0.mask[i]=0 selects vs2[i]; v0 is the selection mask rather than a normal execution mask.
Quick Understanding & Search Notes
VFMERGE.VFM is conditional selection, not arithmetic. The common mistake is reversing the selection direction: mask bit 1 selects the FP scalar, and mask bit 0 selects the vs2 element.
The instruction uses v0 as the merge-selection mask.
The operation applies only to active elements within vl; inactive and tail elements follow the current vma/vta policy.
Except for dedicated mask forms, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
Floating-point operations follow the vector FP rules: normal FP operations use frm rounding and set FP exception flags; fixed-point vxrm does not control them.
Common Usage Scenarios
Conditional Assignment
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfmerge.vfm v1, v2, ft0, v0 # v0[i] ? ft0 : v2[i]».
Ternary Operator
Understand this scenario with real code like «vsetvli t0, a0, e32, m1, ta, ma vfmerge.vfm v1, v2, ft0, v0 # v0[i] ? ft0 : v2[i]».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is R-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Mask is always v0; no other mask register allowed. No vm bit — always masked operation.
vfmerge.vfm is float version of vmerge.vxm. Scalar from f register, not x register.
Vector FP32/FP64 operations require matching scalar F/D support; FP16 operation is not implied by V alone.