How is VRSUB.VI different from VSUB?
VRSUB is reverse subtraction: scalar or immediate minus vs2. VSUB computes vs2 minus the other operand.
VRSUB.VI
RISC-V VRSUB.VI Instruction Details
Instruction ManualI-typeSubtract vector elements from a sign-extended immediate.
Instruction Syntax
vrsub.vi vd, vs2, imm, vm
Operand Breakdown
Destination rd: general-purpose register receiving the result.
Source rs1: register holding the first operand.
Immediate imm: 12-bit signed value, sign-extended before operation with rs1.
VVector IntegerArithmetic
Related Search Terms
Instruction Behavior
VRSUB.VI computes signext(imm) - vs2[i] for active elements and writes the low SEW bits to vd.
Quick Understanding & Search Notes
VRSUB.VI reverses the operand direction of VSUB and computes scalar/immediate minus each element.
Results wrap at SEW width and do not raise integer overflow exceptions.
The VI form uses a 5-bit signed immediate extended to SEW.
Use VSUB.VX, not VRSUB.VX, when you need vector minus scalar.
Common Usage Scenarios
Symmetric Range
Understand this scenario with real code like «vrsub.vi v8, v12, 7, v0.t».
Complement
Understand this scenario with real code like «vrsub.vi v8, v12, 7, v0.t».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is I-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Order reversed: imm/scalar-vector (not vector-imm/scalar)