What is the immediate range for VRSUB.VI?
The VI form uses a 5-bit signed immediate, ranging from -16 to 15, sign-extended before the operation.
VRSUB.VI
RISC-V VRSUB.VI Instruction Details
Instruction ManualOPIVI (OP-V)Subtract vector elements from a sign-extended immediate.
Instruction Syntax
vrsub.vi vd, vs2, imm[, v0.t]
Operand Breakdown
Syntax: vrsub.vi vd, vs2, imm[, v0.t]; omit the mask for vm=1, include it for vm=0. 32-bit OP-V: opcode=1010111, funct3=011 (OPIVI), funct6=000011.
Compute sign-extended simm5 (-16..15) minus vs2[i], keeping low SEW bits without an arithmetic-overflow trap.
Body is vstart≤i<vl; only mask-enabled body elements execute, with inactive/tail following vma/vta. Prestart is unchanged; vl=0 or vstart≥vl updates no destination elements.
Same-width sources/destination may overlap; an ordinary masked vd cannot be v0. When v0 supplies EEW=1 mask/borrow bits it cannot also supply data; source groups cannot read a register with different EEWs. Group starts align to EMUL, EMUL≤8.
Require RV32/RV64 V 1.0, enabled vector state and valid supported vtype/SEW. The animation fixes m1 and vstart=0; VLEN=4096. Only body is shown; steps are not processor cycles.
VVector IntegerArithmetic
Instruction Behavior
VRSUB.VI computes signext(imm) - vs2[i] for active elements and writes the low SEW bits to vd.
VRSUB.VI Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VRSUB subtracts vs2 from the second source, wraps at SEW, and writes vd.
Instruction input
vrsub.vi
Require V 1.0, enabled vector state and valid supported vtype/SEW; fix LMUL=m1 and vstart=0. Fix VLEN=4096 and VLMAX=4096/16=256; equal-width sources/destination may overlap. Compute sign-extended simm5 (-16..15) minus vs2[i], keeping low SEW bits. When v0 supplies the EEW=1 mask/borrow bits it cannot also supply data. Enter nonnegative element bit patterns. VL=0 updates no destination bits. Only body is shown without definite inactive/tail values; teaching stages are not processor cycles.
Execution Context
immediate value
7 -> 0x0007
5-bit signed imm is sign-extended to SEWOP-V encodingvrsub.vi
funct6
000011
vm
0
vs2
01000
simm5
00111
funct3
011
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
imm
0x0007
0x0007
0x0007
0x0007
0x0007
0x0007
0x0007
0x0007
-
-
-
-
-
-
-
-
v8
0x00fa
0x010b
0x011c
0x012d
0x013e
0x014f
0x0160
0x0171
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vrsub.vi uses OP-V encoding. The animation places fixed fields, register fields, vm, and the imm field in one encoding strip.
This animation shows OP-V field decode, reverse subtraction, execution masking, and vd writeback; teaching stages are not processor cycles.
Quick Understanding & Search Notes
VRSUB.VI computes sign-extended imm - vs2[i] for each active element. The VI form uses a 5-bit signed immediate in the range -16 through 15.
Body is vstart≤i<vl; vm=0 uses v0 as execution mask. Inactive/tail follow vma/vta; vl=0 or vstart≥vl updates no destination elements.
VRSUB.VI is single-width integer reverse subtraction; the left operand is the sign-extended value of a 5-bit signed immediate.
The `.vi` direction is imm - vs2; use VADD.VI for vector plus immediate, and VSUB has no vector-minus-immediate VI form.
In OP-V encoding, opcode=1010111 and VRSUB uses funct6=000011; the `.vi` form is selected by funct3=011, with simm5 encoding the immediate.
The result wraps to the low SEW bits and provides no borrow flag or overflow trap.
Vector Execution Context
Syntax: vrsub.vi vd, vs2, imm[, v0.t]; omit the mask for vm=1, include it for vm=0. 32-bit OP-V: opcode=1010111, funct3=011 (OPIVI), funct6=000011.
Compute sign-extended simm5 (-16..15) minus vs2[i], keeping low SEW bits without an arithmetic-overflow trap.
Body is vstart≤i<vl; only mask-enabled body elements execute, with inactive/tail following vma/vta. Prestart is unchanged; vl=0 or vstart≥vl updates no destination elements.
Same-width sources/destination may overlap; an ordinary masked vd cannot be v0. When v0 supplies EEW=1 mask/borrow bits it cannot also supply data; source groups cannot read a register with different EEWs. Group starts align to EMUL, EMUL≤8.
Require RV32/RV64 V 1.0, enabled vector state and valid supported vtype/SEW. The animation fixes m1 and vstart=0; VLEN=4096. Only body is shown; steps are not processor cycles.
Common Usage Scenarios
Elementwise reverse subtraction
Assume enabled V/VS, valid m1, supported SEW, VLEN=4096 and XLEN=64, vl=4, vstart=0 and initialized sources, v0.mask[0..3]=1111. SEW=8, imm=7, v12=[10,0,255,7] → v8=[253,7,8,0]. Inactive/tail follow vma/vta. vl=0 leaves vd unchanged.
Vector negation
Assume enabled V/VS, valid m1, supported SEW, VLEN=4096 and XLEN=64, vl=4, vstart=0 and initialized sources, v0.mask[0..3]=1111. SEW=8, imm=7, v12=[10,0,255,7] → v8=[253,7,8,0]. Inactive/tail follow vma/vta. vl=0 leaves vd unchanged.
Pre-Use Checklist
Syntax Check
- Syntax: vrsub.vi vd, vs2, imm[, v0.t]; omit the mask for vm=1, include it for vm=0. 32-bit OP-V: opcode=1010111, funct3=011 (OPIVI), funct6=000011.
- Compute sign-extended simm5 (-16..15) minus vs2[i], keeping low SEW bits without an arithmetic-overflow trap.
Semantic Check
- Body is vstart≤i<vl; only mask-enabled body elements execute, with inactive/tail following vma/vta. Prestart is unchanged; vl=0 or vstart≥vl updates no destination elements.
- Same-width sources/destination may overlap; an ordinary masked vd cannot be v0. When v0 supplies EEW=1 mask/borrow bits it cannot also supply data; source groups cannot read a register with different EEWs. Group starts align to EMUL, EMUL≤8.
- Require RV32/RV64 V 1.0, enabled vector state and valid supported vtype/SEW. The animation fixes m1 and vstart=0; VLEN=4096. Only body is shown; steps are not processor cycles.
Pitfalls / Common Confusions
The immediate or scalar is the left operand; vs2[i] is the right operand.
Keep the low SEW bits; ordinary masked inactive/tail elements follow vma/vta.
FAQ
Is there a VSUB.VI form?
Ordinary single-width integer subtraction provides VSUB.VV, VSUB.VX, and reverse-subtract VRSUB.VX/VRSUB.VI; vector minus immediate is not a separate VSUB.VI form.