Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VRSUB.VI
RISC-V VRSUB.VI Instruction Details
Instruction ManualOPIVISubtract vector elements from a sign-extended immediate.
Instruction Syntax
vrsub.vi vd, vs2, imm, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector IntegerArithmetic
Instruction Behavior
VRSUB.VI computes signext(imm) - vs2[i] for active elements and writes the low SEW bits to vd.
VRSUB.VI Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VRSUB subtracts vs2 from the second source, wraps at SEW, and writes vd.
Instruction input
vrsub.vi
immediate value
7 -> 0x0007
5-bit signed imm is sign-extended to SEWOP-V encodingvrsub.vi
funct6
000011
vm
0
vs2
01000
simm5
00111
funct3
011
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
imm
0x0007
0x0007
0x0007
0x0007
0x0007
0x0007
0x0007
0x0007
-
-
-
-
-
-
-
-
v8
0x00fa
0x010b
0x011c
0x012d
0x013e
0x014f
0x0160
0x0171
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vrsub.vi uses OP-V encoding. The animation places fixed fields, register fields, vm, and the imm field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, SEW-width integer reverse subtraction, mask control, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VRSUB.VI computes sign-extended imm - vs2[i] for each active element. The VI form uses a 5-bit signed immediate in the range -16 through 15.
This page follows the official RISC-V V extension: vector instructions operate on body elements within the current vl; vm=0 uses v0 as the execution mask, and SEW, LMUL, mask policy, and tail policy come from the current vtype.
VRSUB.VI is single-width integer reverse subtraction; the left operand is the sign-extended value of a 5-bit signed immediate.
The `.vi` direction is imm - vs2; use VADD.VI for vector plus immediate, and VSUB has no vector-minus-immediate VI form.
In OP-V encoding, opcode=1010111 and VRSUB uses funct6=000011; the `.vi` form is selected by funct3=011, with simm5 encoding the immediate.
The result wraps to the low SEW bits and provides no borrow flag or overflow trap.
Vector Execution Context
When reading VRSUB.VI, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vi: one vector source and a small immediate participate.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Symmetric Range
Understand this scenario with real code like «vrsub.vi v8, v12, 7, v0.t».
Complement
Understand this scenario with real code like «vrsub.vi v8, v12, 7, v0.t».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is OPIVI.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Order reversed: imm/scalar-vector (not vector-imm/scalar)
FAQ
What is the immediate range for VRSUB.VI?
The VI form uses a 5-bit signed immediate, ranging from -16 to 15, sign-extended before the operation.
Is there a VSUB.VI form?
Ordinary single-width integer subtraction provides VSUB.VV, VSUB.VX, and reverse-subtract VRSUB.VX/VRSUB.VI; vector minus immediate is not a separate VSUB.VI form.