How is VRSUB.VX different from VSUB.VX?
VRSUB.VX computes x[rs1] - vs2[i], while VSUB.VX computes vs2[i] - x[rs1]. Subtraction is not commutative, so the results usually differ.
VRSUB.VX
RISC-V VRSUB.VX Instruction Details
Instruction ManualOPIVX (OP-V)Subtract vector elements from a scalar register.
Instruction Syntax
vrsub.vx vd, vs2, rs1[, v0.t]
Operand Breakdown
Syntax: vrsub.vx vd, vs2, rs1[, v0.t]; omit the mask for vm=1, include it for vm=0. 32-bit OP-V: opcode=1010111, funct3=100 (OPIVX), funct6=000011.
Compute x[rs1], taking low SEW bits when XLEN>SEW, sign-extending when XLEN<SEW, with x0 supplying zero minus vs2[i], keeping low SEW bits without an arithmetic-overflow trap.
Body is vstart≤i<vl; only mask-enabled body elements execute, with inactive/tail following vma/vta. Prestart is unchanged; vl=0 or vstart≥vl updates no destination elements.
Same-width sources/destination may overlap; an ordinary masked vd cannot be v0. When v0 supplies EEW=1 mask/borrow bits it cannot also supply data; source groups cannot read a register with different EEWs. Group starts align to EMUL, EMUL≤8.
Require RV32/RV64 V 1.0, enabled vector state and valid supported vtype/SEW. The animation fixes m1 and vstart=0; VLEN=4096. Only body is shown; steps are not processor cycles.
VVector IntegerArithmetic
Instruction Behavior
VRSUB.VX computes x[rs1] - vs2[i] for active elements and writes the low SEW bits to vd.
VRSUB.VX Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VRSUB subtracts vs2 from the second source, wraps at SEW, and writes vd.
Instruction input
vrsub.vx
Require V 1.0, enabled vector state and valid supported vtype/SEW; fix LMUL=m1 and vstart=0. Fix VLEN=4096 and VLMAX=4096/16=256; equal-width sources/destination may overlap. Compute the scalar converted by XLEN/SEW minus vs2[i], keeping low SEW bits. x0 supplies zero. When v0 supplies the EEW=1 mask/borrow bits it cannot also supply data. Enter nonnegative element bit patterns. VL=0 updates no destination bits. Only body is shown without definite inactive/tail values; teaching stages are not processor cycles.
Execution Context
OP-V encodingvrsub.vx
funct6
000011
vm
0
vs2
01000
rs1
01011
funct3
100
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
x11
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
-
-
-
-
-
-
-
-
v8
0x00fa
0x010b
0x011c
0x012d
0x013e
0x014f
0x0160
0x0171
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vrsub.vx uses OP-V encoding. The animation places fixed fields, register fields, vm, and the rs1 field in one encoding strip.
This animation shows OP-V field decode, reverse subtraction, execution masking, and vd writeback; teaching stages are not processor cycles.
Quick Understanding & Search Notes
VRSUB.VX is reverse subtraction: each active element computes x[rs1] - vs2[i]. It is not a synonym for VSUB.VX; the operand order is reversed.
Body is vstart≤i<vl; vm=0 uses v0 as execution mask. Inactive/tail follow vma/vta; vl=0 or vstart≥vl updates no destination elements.
VRSUB is single-width integer reverse subtraction; in the VX form the left operand comes from integer register rs1.
The `.vx` direction is rs1 - vs2; use VSUB.VX for vs2 - rs1.
In OP-V encoding, opcode=1010111 and VRSUB uses funct6=000011; the `.vx` form is selected by funct3=100.
The result wraps to the low SEW bits and provides no borrow flag or overflow trap.
XLEN>SEW uses the low SEW scalar bits; XLEN<SEW sign-extends to SEW. rs1=x0 supplies zero.
Vector Execution Context
Syntax: vrsub.vx vd, vs2, rs1[, v0.t]; omit the mask for vm=1, include it for vm=0. 32-bit OP-V: opcode=1010111, funct3=100 (OPIVX), funct6=000011.
Compute x[rs1], taking low SEW bits when XLEN>SEW, sign-extending when XLEN<SEW, with x0 supplying zero minus vs2[i], keeping low SEW bits without an arithmetic-overflow trap.
Body is vstart≤i<vl; only mask-enabled body elements execute, with inactive/tail following vma/vta. Prestart is unchanged; vl=0 or vstart≥vl updates no destination elements.
Same-width sources/destination may overlap; an ordinary masked vd cannot be v0. When v0 supplies EEW=1 mask/borrow bits it cannot also supply data; source groups cannot read a register with different EEWs. Group starts align to EMUL, EMUL≤8.
Require RV32/RV64 V 1.0, enabled vector state and valid supported vtype/SEW. The animation fixes m1 and vstart=0; VLEN=4096. Only body is shown; steps are not processor cycles.
Common Usage Scenarios
Elementwise reverse subtraction
Assume enabled V/VS, valid m1, supported SEW, VLEN=4096 and XLEN=64, vl=4, vstart=0 and initialized sources, v0.mask[0..3]=1111. SEW=8, x5=7, v12=[10,0,255,7] → v8=[253,7,8,0]. Inactive/tail follow vma/vta. vl=0 leaves vd unchanged.
Vector negation
Assume enabled V/VS, valid m1, supported SEW, VLEN=4096 and XLEN=64, vl=4, vstart=0 and initialized sources, v0.mask[0..3]=1111. SEW=8, x5=7, v12=[10,0,255,7] → v8=[253,7,8,0]. Inactive/tail follow vma/vta. vl=0 leaves vd unchanged.
Pre-Use Checklist
Syntax Check
- Syntax: vrsub.vx vd, vs2, rs1[, v0.t]; omit the mask for vm=1, include it for vm=0. 32-bit OP-V: opcode=1010111, funct3=100 (OPIVX), funct6=000011.
- Compute x[rs1], taking low SEW bits when XLEN>SEW, sign-extending when XLEN<SEW, with x0 supplying zero minus vs2[i], keeping low SEW bits without an arithmetic-overflow trap.
Semantic Check
- Body is vstart≤i<vl; only mask-enabled body elements execute, with inactive/tail following vma/vta. Prestart is unchanged; vl=0 or vstart≥vl updates no destination elements.
- Same-width sources/destination may overlap; an ordinary masked vd cannot be v0. When v0 supplies EEW=1 mask/borrow bits it cannot also supply data; source groups cannot read a register with different EEWs. Group starts align to EMUL, EMUL≤8.
- Require RV32/RV64 V 1.0, enabled vector state and valid supported vtype/SEW. The animation fixes m1 and vstart=0; VLEN=4096. Only body is shown; steps are not processor cycles.
Pitfalls / Common Confusions
The immediate or scalar is the left operand; vs2[i] is the right operand.
Keep the low SEW bits; ordinary masked inactive/tail elements follow vma/vta.
FAQ
How does VRSUB.VX handle underflow?
The result keeps the low SEW bits and wraps at SEW width, with no integer trap or borrow flag.