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VSLIDEDOWN.VI

RISC-V VSLIDEDOWN.VI Instruction Details

Instruction ManualV-type

Slide vector elements toward lower indexes.

Instruction Syntax

vslidedown.vi vd, vs2, uimm[, v0.t]
Operand Breakdown
vd/vs2 are SEW/LMUL vector groups with starts aligned to EMUL. Equal-width source/destination overlap is allowed. uimm is a zero-extended 5-bit element offset, 0–31.
32-bit OP-V: funct6=001111 at bits31:26, vm at bit25, vs2 at bits24:20, uimm at bits19:15, funct3=011 at bits14:12, vd at bits11:7, opcode=1010111 at bits6:0.
Active vd[i]=vs2[i+OFFSET]; the source index may exceed vl, but zero is returned only upon reaching VLMAX. This is not a memory address or byte offset.
Optional v0.t means vm=0; omission means vm=1. Masked vd cannot contain v0, which cannot supply both EEW=1 mask and SEW data. Prestart is unchanged; inactive/tail follow vma/vta, with the slideup region below both OFFSET and vl always unchanged.
Require V 1.0, enabled vector state and valid supported vtype/SEW. vstart>=vl (including vl=0) leaves all destination elements unchanged. Examples assume LMUL=m1, SEW=16, vl=8, vstart=0 and initialized sources, scalars and v0; animation stages are for teaching.
VVector PermutationSlide
Related Search Terms
vslidedown.vi instructionRISC-V vslidedown.vivslidedown.vi encodingRVV slide downvector zero fillvslidedown immediate

Instruction Behavior

VSLIDEDOWN.VI moves vs2 elements by offset uimm toward lower indexes into vd. A source index outside VLMAX writes zero to the destination element.

VSLIDEDOWN.VI Decode And Execute Animation

Starts from OP-V encoding fields, then shows how VSLIDEDOWN reads higher-numbered source elements by OFFSET; destination elements whose source index is >= VLMAX receive zero.

Instruction input
vslidedown.vi

Require V 1.0, enabled vector state, and valid supported vtype/SEW. Fix LMUL=m1 and vstart=0; this teaching configuration has VLEN=VLMAX×SEW=256, at least 128 bits. Changing SEW/VLMAX switches configurations. Only body is shown; inactive/tail values follow vma/vta without definite values. VL=0 updates no destination elements, including tails. With masking, vd/vs2 cannot be v0. Equal-width vd/vs2 may overlap. OFFSET is a full unsigned XLEN value or zero-extended 5-bit immediate; source indexes ≥VLMAX return zero. Steps are teaching stages, not processor cycles.

Execution Context
immediate value
3 -> OFFSET 3
5-bit unsigned uimm is zero-extended as the element OFFSET, not truncated by SEW

The teaching model fixes LMUL=m1 and vstart=0 and shows only body elements in the selected VL. In ordinary masked forms, inactive and tail elements follow vtype.vma/vta and the result row does not invent a definite value; VADC/VMADC/VSBC/VMSBC execute every body element, with v0 bits used only as carry/borrow-in.

OP-V encodingvslidedown.vi
funct6
001111
vm
0
vs2
01000
uimm
00011
funct3
011
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x0001
0x0004
0x0007
0x000a
0x000d
0x0010
0x0013
0x0016
i+OFF
i+OFF
i+OFF
i+OFF
i+OFF
i+OFF
i+OFF
i+OFF
imm
0x0003
0x0003
0x0003
0x0003
0x0003
0x0003
0x0003
0x0003
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step

Show OP-V 32-bit encoding fields

vslidedown.vi uses OP-V encoding. The animation places fixed fields, register fields, vm, and the uimm field in one encoding strip.

This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, element-index/packing/select/move rearrangement integer slide down, boundary/selection rules, and vd writeback. It does not model pipelines, caches, or timing.

Quick Understanding & Search Notes

vslidedown.vi uses uimm as OFFSET: active element i reads vs2[i+OFFSET]; if i+OFFSET >= VLMAX, the result is zero.

OP-V encoding uses funct6=001111 and funct3=011 for vslidedown.vi.
OFFSET is a 5-bit zero-extended immediate.
vslidedown does not have the vslideup destination/source non-overlap restriction.
Require an enabled vector extension/state, valid vtype, and supported SEW. When vstart>=vl (including vl=0), the entire destination is unchanged. Active elements satisfy vstart<=i<vl and are mask-enabled; inactive/tail elements follow vma/vta.
Omitting the mask operand selects vm=1; v0.t selects vm=0 and the v0 bit at each destination index. A masked vd cannot overlap v0, and v0 cannot also supply SEW data.
OFFSET is an unsigned element-index offset, not bytes: x[rs1] uses full XLEN and uimm is 0..31. Source elements beyond vl but below VLMAX may be read; zero fill starts at source index VLMAX.
The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture, Version 20260120: Official Release — §31.16.3 Vector Slide Instructions

Vector Execution Context

vd/vs2 are SEW/LMUL vector groups with starts aligned to EMUL. Equal-width source/destination overlap is allowed. uimm is a zero-extended 5-bit element offset, 0–31.

32-bit OP-V: funct6=001111 at bits31:26, vm at bit25, vs2 at bits24:20, uimm at bits19:15, funct3=011 at bits14:12, vd at bits11:7, opcode=1010111 at bits6:0.

Active vd[i]=vs2[i+OFFSET]; the source index may exceed vl, but zero is returned only upon reaching VLMAX. This is not a memory address or byte offset.

Optional v0.t means vm=0; omission means vm=1. Masked vd cannot contain v0, which cannot supply both EEW=1 mask and SEW data. Prestart is unchanged; inactive/tail follow vma/vta, with the slideup region below both OFFSET and vl always unchanged.

Require V 1.0, enabled vector state and valid supported vtype/SEW. vstart>=vl (including vl=0) leaves all destination elements unchanged. Examples assume LMUL=m1, SEW=16, vl=8, vstart=0 and initialized sources, scalars and v0; animation stages are for teaching.

The RISC-V Instruction Set Manual, Volume I: Unprivileged Architecture — Version 20260120, Chapter 31

Common Usage Scenarios

Register element rearrangement

Understand this scenario with real code like «vslidedown.vi v8, v12, 3, v0.t».

Pre-Use Checklist

Syntax Check
  • vd/vs2 are SEW/LMUL vector groups with starts aligned to EMUL. Equal-width source/destination overlap is allowed. uimm is a zero-extended 5-bit element offset, 0–31.
  • 32-bit OP-V: funct6=001111 at bits31:26, vm at bit25, vs2 at bits24:20, uimm at bits19:15, funct3=011 at bits14:12, vd at bits11:7, opcode=1010111 at bits6:0.
Semantic Check
  • Active vd[i]=vs2[i+OFFSET]; the source index may exceed vl, but zero is returned only upon reaching VLMAX. This is not a memory address or byte offset.
  • Optional v0.t means vm=0; omission means vm=1. Masked vd cannot contain v0, which cannot supply both EEW=1 mask and SEW data. Prestart is unchanged; inactive/tail follow vma/vta, with the slideup region below both OFFSET and vl always unchanged.
  • Require V 1.0, enabled vector state and valid supported vtype/SEW. vstart>=vl (including vl=0) leaves all destination elements unchanged. Examples assume LMUL=m1, SEW=16, vl=8, vstart=0 and initialized sources, scalars and v0; animation stages are for teaching.

Pitfalls / Common Confusions

OFFSET is a 5-bit zero-extended immediate.
For active destinations only, i+OFFSET>=VLMAX writes zero; inactive/tail elements follow vma/vta.
Unlike vslideup, vslidedown has no destination/source non-overlap restriction.

FAQ

When does vslidedown.vi write zero?

When the source index i+OFFSET for an active element is greater than or equal to VLMAX, that destination element writes zero by the official rule.

Does VSLIDEDOWN.VI access memory?

No. It rearranges elements within vector register groups and performs no memory load or store.