Check vl first
The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.
VSLIDEDOWN.VI
RISC-V VSLIDEDOWN.VI Instruction Details
Instruction ManualI-typeSlide vector elements toward lower indexes.
Instruction Syntax
vslidedown.vi vd, vs2, uimm, vm
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector PermutationSlide
Instruction Behavior
VSLIDEDOWN.VI moves vs2 elements by offset uimm toward lower indexes into vd. A source index outside VLMAX writes zero to the destination element.
VSLIDEDOWN.VI Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VSLIDEDOWN reads higher-numbered source elements by OFFSET; destination elements whose source index is >= VLMAX receive zero.
Instruction input
vslidedown.vi
immediate value
3 -> OFFSET 3
5-bit unsigned uimm is zero-extended as the element OFFSET, not truncated by SEWOP-V encodingvslidedown.vi
funct6
001111
vm
0
vs2
01000
uimm
00011
funct3
011
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x0001
0x0004
0x0007
0x000a
0x000d
0x0010
0x0013
0x0016
i+OFF
i+OFF
i+OFF
i+OFF
i+OFF
i+OFF
i+OFF
i+OFF
imm
0x0003
0x0003
0x0003
0x0003
0x0003
0x0003
0x0003
0x0003
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vslidedown.vi uses OP-V encoding. The animation places fixed fields, register fields, vm, and the uimm field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, element-index/packing/select/move rearrangement integer slide down, boundary/selection rules, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
vslidedown.vi uses uimm as OFFSET: active element i reads vs2[i+OFFSET]; if i+OFFSET >= VLMAX, the result is zero.
OP-V encoding uses funct6=001111 and funct3=011 for vslidedown.vi.
OFFSET is a 5-bit zero-extended immediate.
vslidedown does not have the vslideup destination/source non-overlap restriction.
Vector Execution Context
When reading VSLIDEDOWN.VI, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. .vi: one vector source and a small immediate participate.
Then check vtype
The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.
Then check vm/v0
For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.
Common Usage Scenarios
Data Shift
Understand this scenario with real code like «vslidedown.vi v8, v12, 3, v0.t».
Convolution
Understand this scenario with real code like «vslidedown.vi v8, v12, 3, v0.t».
Shift Register
Understand this scenario with real code like «vslidedown.vi v8, v12, 3, v0.t».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is I-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
OFFSET is a 5-bit zero-extended immediate.
When i+OFFSET >= VLMAX, the result element is zero.
Unlike vslideup, vslidedown has no destination/source non-overlap restriction.
FAQ
When does vslidedown.vi write zero?
When the source index i+OFFSET for an active element is greater than or equal to VLMAX, that destination element writes zero by the official rule.
Does VSLIDEDOWN.VI access memory?
No. It only rearranges vector-register elements or inserts a scalar-register value; memory loads and stores are handled by vector load/store instructions.