How is VSM.V different from VSE8.V?
VSM.V stores ceil(vl/8) packed mask bytes; VSE8.V stores 8-bit data elements.
VSM.V
RISC-V VSM.V Instruction Details
Instruction ManualVector StoreStore ceil(vl/8) complete source-register bytes starting at x[rs1].
Instruction Syntax
vsm.v vs3, (rs1)
Operand Breakdown
vs3 is one source vector register (v0–v31); rs1 is an integer base register, with x0 supplying address 0.
32-bit STORE-FP: opcode=0100111, nf=000, mew=0, mop=00, vm=1, sumop=01011, width=000; vs3 is bits11:7 and rs1 is bits19:15. No v0.t operand.
EEW=8, EMUL=1, evl=ceil(vl/8). Store complete source bytes starting at byte vstart. Source bit i maps to bit i mod 8 at x[rs1]+floor(i/8); final-byte source bits with i≥vl are also stored.
vstart counts bytes; vstart≥evl (including vl=0) makes no access. Unit stride does not guarantee byte access order; accesses may trap. Examples assume vstart=0 and writable memory; the source register stays unchanged.
Require V 1.0, enabled vector state and valid supported vtype/SEW; normal completion resets vstart=0. Animation stages are teaching steps, not processor cycles.
VVector MemoryMask Operations
Instruction Behavior
VSM.V is an unmasked unit-stride mask store with EEW=8 and EMUL=1. Source bit i maps to bit i mod 8 of byte floor(i/8). Source bits at indexes ≥vl in the final byte are also stored, without automatic zeroing.
VSM.V Decode And Execute Animation
Decode the packed mask store, then compute each element address as x[rs1] + floor(i/8).
Instruction input
vsm.v
Execution Context
Execution context: packed mask byte count=ceil(VL/8)=2; mask bit i is bit i mod 8 of byte floor(i/8). This form is fixed unmasked with vm=1 in the encoding, and the animation fixes vstart=0 (mask loads and stores count vstart in bytes), LMUL=m1. These are not assembly syntax operands.
Teaching scope: this animation shows only a no-exception packed-mask transfer with vstart=0. Mask loads and stores count vstart in bytes; EEI-defined access-fault or trap outcomes are not modeled by this example.
Teaching context: V 1.0, enabled VS, valid vtype, VLEN=4096, SEW=8, LMUL=m1, vstart=0, no access faults. EEW=8, EMUL=1, vm=1; rs1=x0 fixes the base at 0. VL=0 makes no access; otherwise store all ceil(VL/8) bytes, including all source bits in the last byte. Per-bit stages explain mapping, not access order or processor cycles.
Encoding fieldsvsm.v / STORE-FP
31..29
nf
000
28
mew
0
27..26
mop
00
25
vm
1
24..20
sumop
01011
19..15
rs1
01010
14..12
width
000
11..7
vd/vs3
00000
6..0
opcode
0100111
Address and data pathbytes=2, byte=floor(i/8), addr=0x8000+byte
i=0
i=1
i=2
i=3
i=4
i=5
i=6
i=7
i=8
i=9
i=10
i=11
i=12
i=13
i=14
i=15
byte.bit
b0.0
b0.1
b0.2
b0.3
b0.4
b0.5
b0.6
b0.7
b1.0
b1.1
b1.2
b1.3
b1.4
b1.5
b1.6
b1.7
addr
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8001
0x8001
0x8001
0x8001
0x8001
0x8001
0x8001
0x8001
v0 bit
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
memory write
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
byte 0 @ 0x8000
0x7b
byte 1 @ 0x8001
0xef
Step 1 / 22
Show vector memory instruction encoding
The animation starts from the 32-bit vector memory encoding and shows the official bit fields: nf, mew, mop, vm, rs2/vs2 or lumop/sumop, width, register fields, and opcode.
Quick Understanding & Search Notes
With VL=9 and vstart=0, store 2 complete bytes: source-register bits 0..15. The source register is unchanged.
The access size is ceil(vl/8) contiguous bytes addressed from x[rs1].
Source mask bit i is written to bit i mod 8 of byte floor(i/8).
The encoding uses the vector-store format with mop=00, width=000, sumop=01011, and vm=1.
A valid vtype (vill=0) constrains vl; VL=0 makes no access, and normal completion resets vstart=0.
Vector Execution Context
vs3 is one source vector register (v0–v31); rs1 is an integer base register, with x0 supplying address 0.
32-bit STORE-FP: opcode=0100111, nf=000, mew=0, mop=00, vm=1, sumop=01011, width=000; vs3 is bits11:7 and rs1 is bits19:15. No v0.t operand.
EEW=8, EMUL=1, evl=ceil(vl/8). Store complete source bytes starting at byte vstart. Source bit i maps to bit i mod 8 at x[rs1]+floor(i/8); final-byte source bits with i≥vl are also stored.
vstart counts bytes; vstart≥evl (including vl=0) makes no access. Unit stride does not guarantee byte access order; accesses may trap. Examples assume vstart=0 and writable memory; the source register stays unchanged.
Require V 1.0, enabled vector state and valid supported vtype/SEW; normal completion resets vstart=0. Animation stages are teaching steps, not processor cycles.
Common Usage Scenarios
Save packed mask data
Assume enabled V/VS, valid supported m1, VLEN=4096, XLEN=64, vstart=0 and initialized sources with successful memory writes. VL=9, v0 bits[0..15]=1000000000000001, a0=0x8000 → [0x8000]=0x01, [0x8001]=0x80. The bit string is in increasing index order; the complete final byte includes source bits beyond VL.
Vector mask save/restore
Assume enabled V/VS, valid supported m1, VLEN=4096, XLEN=64, vstart=0 and initialized sources with successful memory writes. VL=9, v0 bits[0..15]=1000000000000001, a0=0x8000 → [0x8000]=0x01, [0x8001]=0x80. The bit string is in increasing index order; the complete final byte includes source bits beyond VL.
Mask-state save during context switching
Assume enabled V/VS, valid supported m1, VLEN=4096, XLEN=64, vstart=0 and initialized sources with successful memory writes. VL=9, v0 bits[0..15]=1000000000000001, a0=0x8000 → [0x8000]=0x01, [0x8001]=0x80. The bit string is in increasing index order; the complete final byte includes source bits beyond VL.
Pre-Use Checklist
Syntax Check
- vs3 is one source vector register (v0–v31); rs1 is an integer base register, with x0 supplying address 0.
- 32-bit STORE-FP: opcode=0100111, nf=000, mew=0, mop=00, vm=1, sumop=01011, width=000; vs3 is bits11:7 and rs1 is bits19:15. No v0.t operand.
Semantic Check
- EEW=8, EMUL=1, evl=ceil(vl/8). Store complete source bytes starting at byte vstart. Source bit i maps to bit i mod 8 at x[rs1]+floor(i/8); final-byte source bits with i≥vl are also stored.
- vstart counts bytes; vstart≥evl (including vl=0) makes no access. Unit stride does not guarantee byte access order; accesses may trap. Examples assume vstart=0 and writable memory; the source register stays unchanged.
- Require V 1.0, enabled vector state and valid supported vtype/SEW; normal completion resets vstart=0. Animation stages are teaching steps, not processor cycles.
Pitfalls / Common Confusions
The effective transfer size is ceil(vl/8) bytes and is independent of ordinary SEW/LMUL data-element width.
The syntax names a source vs3 mask register; it is not restricted to v0.
VSM.V is an unmasked form with vm=1 in the encoding; no ordinary v0.t execution mask disables individual lanes.
vstart counts bytes; vstart≥ceil(vl/8) makes no memory access. Vector memory accesses may still trap.
FAQ
Can VSM.V store only v0?
No. vs3 may name any vector register v0–v31.