Does VSM.V store SEW-width elements?
No. It stores mask bits packed into a byte sequence.
VSM.V
RISC-V VSM.V Instruction Details
Instruction ManualS-typeStore a mask register to memory as a packed bitmap.
Instruction Syntax
vsm.v vs3, (rs1)
Operand Breakdown
Source rs2: register holding data to write to memory.
Base rs1: register holding the base address.
Immediate offset: 12-bit signed value added to rs1 for the final address.
VVector Operations
Related Search Terms
Instruction Behavior
VSM.V stores mask bits from vs3 to memory at x[rs1] as consecutive bytes; the number of stored bytes is ceil(vl/8).
Quick Understanding & Search Notes
VSM.V is a dedicated mask store; it does not store ordinary data elements by SEW.
The memory layout is a packed bitmap whose length is determined by vl.
This form has no ordinary vm mask operand.
Unlike VSE8.V, the data source is mask bits.
Common Usage Scenarios
Save/restore vector mask
Understand this scenario with real code like «vsm.v v0, (a0)».
Context switching
Understand this scenario with real code like «vsm.v v0, (a0)».
Mask debugging
Understand this scenario with real code like «vsm.v v0, (a0)».
Pre-Use Checklist
Syntax Check
- Confirm the current instruction format is S-type.
- Confirm the operand order matches the example.
Semantic Check
- Ensure the destination register usage is compatible with the calling convention.
- Confirm this is not the lower-level form of a pseudo-instruction expansion.
Pitfalls / Common Confusions
Effective length is ceil(vl/8) bytes and is independent of SEW/LMUL.
The syntax names source register vs3; it is not restricted to v0.