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VSM.V

RISC-V VSM.V Instruction Details

Instruction ManualV-type

Pack the VL bits from the source mask register into ceil(vl/8) contiguous bytes and store them starting at x[rs1].

Instruction Syntax

vsm.v vs3, (rs1)
Operand Breakdown
vd: destination vector register group.
vs2/vs1 or scalar source: selected by suffixes such as .vv, .vx, .vi, or .vf.
vm: when present, vm=0 uses v0 as the execution mask and vm=1 is unmasked.
VVector MemoryMask Operations
Related Search Terms
VSM.V instructionRISC-V VSM.Vvsm.v syntaxRVV mask storepacked mask storevsm.v encodingceil vl 8

Instruction Behavior

VSM.V is the RISC-V V extension unit-stride mask store. It places source mask bit i into bit i mod 8 of byte floor(i/8) and stores ceil(vl/8) packed bytes. The instruction stores mask bits, not ordinary vector elements using SEW.

VSM.V Decode And Execute Animation

Decode the packed mask store, then compute each element address as x[rs1] + floor(i/8).

Instruction input
vsm.v
Execution context: packed mask byte count=ceil(VL/8)=2; mask bit i is bit i mod 8 of byte floor(i/8). This form is fixed unmasked with vm=1 in the encoding, LMUL=m1. These are not assembly syntax operands.
Encoding fieldsvsm.v / STORE-FP
31..29
nf
000
28
mew
0
27..26
mop
00
25
vm
1
24..20
sumop
01011
19..15
rs1
01010
14..12
width
000
11..7
vd/vs3
00000
6..0
opcode
0100111
Address and data pathbytes=2, byte=floor(i/8), addr=0x8000+byte
i=0
i=1
i=2
i=3
i=4
i=5
i=6
i=7
i=8
i=9
i=10
i=11
i=12
i=13
i=14
i=15
byte.bit
b0.0
b0.1
b0.2
b0.3
b0.4
b0.5
b0.6
b0.7
b1.0
b1.1
b1.2
b1.3
b1.4
b1.5
b1.6
b1.7
addr
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8001
0x8001
0x8001
0x8001
0x8001
0x8001
0x8001
0x8001
v0 bit
1
1
0
1
1
1
1
0
1
1
1
1
0
1
1
1
memory write
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
...
byte 0 @ 0x8000
0x7b
byte 1 @ 0x8001
0xef
Step 1 / 22

Show vector memory instruction encoding

The animation starts from the 32-bit vector memory encoding and shows the official bit fields: nf, mew, mop, vm, rs2/vs2 or lumop/sumop, width, register fields, and opcode.

Quick Understanding & Search Notes

VSM.V compresses a mask register into a byte stream: with VL=16 it writes only 2 bytes, one bit contributed by each lane.

The access size is ceil(vl/8) contiguous bytes addressed from x[rs1].
Source mask bit i is written to bit i mod 8 of byte floor(i/8).
The encoding uses the vector-store format with mop=00, width=000, sumop=01011, and vm=1.
RISC-V Unprivileged ISA Manual: V Standard Extension for Vector Operations

Vector Execution Context

When reading VSM.V, do not stop at the mnemonic. Official V-extension semantics also depend on the current vl, vtype, and mask state. The suffix and operand form determine whether sources are vector, scalar, or immediate values.

Check vl first

The current vl determines the number of body elements. Typical code executes vsetvli, vsetivli, or vsetvl before this instruction.

Then check vtype

The current vtype supplies SEW, LMUL, tail policy, and mask policy; these affect element width, register-group size, and inactive/tail destination elements.

Then check vm/v0

For ordinary vector instructions with vm, vm=0 uses v0 as the execution mask and vm=1 is unmasked. A few forms such as VMERGE use v0 as data-selection input.

Official source: RISC-V V Standard Extension for Vector Operations

Common Usage Scenarios

Save packed mask data

Understand this scenario with real code like «vsm.v v0, (a0) # store ceil(vl/8) packed mask bytes».

Vector mask save/restore

Understand this scenario with real code like «vsm.v v0, (a0) # store ceil(vl/8) packed mask bytes».

Mask-state save during context switching

Understand this scenario with real code like «vsm.v v0, (a0) # store ceil(vl/8) packed mask bytes».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is V-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

The effective transfer size is ceil(vl/8) bytes and is independent of ordinary SEW/LMUL data-element width.
The syntax names a source vs3 mask register; it is not restricted to v0.
VSM.V is an unmasked form with vm=1 in the encoding; no ordinary v0.t execution mask disables individual lanes.

FAQ

How is VSM.V different from VSE8.V?

VSM.V stores packed mask bits with a length of ceil(vl/8) bytes; VSE8.V stores 8-bit data elements.

Can VSM.V store only v0?

No. The syntax source operand is vs3, a vector mask register; v0 is only the commonly used mask register.