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VWSUBU.VV

RISC-V VWSUBU.VV Instruction Details

Instruction ManualR-type

VWSUBU.VV performs unsigned widening subtraction.

Instruction Syntax

vwsubu.vv vd, vs2, vs1, vm
Operand Breakdown
Destination rd: register receiving the operation result.
Source rs1: register holding the first operand.
Source rs2: register holding the second operand.
VVector Operations
Related Search Terms
vwsubu.vv instructionvwsubu vvvwsubu.vv RVVvwsubu.vv vl vtypeunsigned widening subtractionvwsubu.vv mask

Instruction Behavior

vwsubu.vv is a V extension unsigned widening subtraction instruction. Both SEW source operands are widened to 2*SEW before subtraction. The result is written to 2*SEW-wide vd.

Quick Understanding & Search Notes

vwsubu.vv is a V extension vector instruction. Active elements are controlled by vl, vtype, vstart, and the optional v0.t mask; it widens operands first and subtracts at 2*SEW width.

Official syntax is `vwsubu.vv vd, vs2, vs1, vm`; without a mask operand it is unmasked, while `, v0.t` updates only selected active elements.
Tail elements and masked-off elements follow the current vtype tail/mask policy; the mnemonic alone does not imply zeroing.
The destination is a wide result, so register-group sizing differs from ordinary vsub.
RISC-V Unprivileged ISA Manual, V standard vector extension

Common Usage Scenarios

Bit Operations & Masks

Understand this scenario with real code like «vwsubu.vv v8, v12, v4, v0.t».

Data Storing

Understand this scenario with real code like «vwsubu.vv v8, v12, v4, v0.t».

Vector Operations

Understand this scenario with real code like «vwsubu.vv v8, v12, v4, v0.t».

Pre-Use Checklist

Syntax Check
  • Confirm the current instruction format is R-type.
  • Confirm the operand order matches the example.
Semantic Check
  • Ensure the destination register usage is compatible with the calling convention.
  • Confirm this is not the lower-level form of a pseudo-instruction expansion.

Pitfalls / Common Confusions

Non-.w forms widen both SEW source operands before subtraction.
The result is a 2*SEW integer subtraction; it does not use vxrm and does not set vxsat.
The destination group is wider and must satisfy V extension EMUL and overlap constraints.

FAQ

What determines the element count for vwsubu.vv?

The current vl and vtype determine it, with vstart, LMUL, SEW, mask state, and tail policy also affecting execution.

Does vwsubu.vv always process the whole vector register?

No. V instructions operate on active elements; register grouping and inactive-element behavior are controlled by vtype and policy bits.