How is VWSUBU.VX different from ordinary subtraction?
VWSUBU.VX zero-extends SEW source elements and produces a 2*SEW-wide result; ordinary single-width vector subtraction writes only a SEW-wide result.
VWSUBU.VX
RISC-V VWSUBU.VX Instruction Details
Instruction ManualV-typeVWSUBU.VX performs unsigned widening subtract; SEW source elements are zero-extended and written as 2*SEW-wide results.
Instruction Syntax
vwsubu.vx vd, vs2, rs1, vm
Operand Breakdown
vd has EEW=2*SEW and EMUL=2*LMUL<=8; vs2 is a SEW/LMUL narrow source, and the second source is rs1 converted to SEW. Wide groups align to their size.
32-bit OP-V: opcode=1010111, funct6=110010, funct3=110 (OPMVX); vm bit25, vs2 bits24:20, rs1 bits19:15, vd bits11:7. Optional v0.t means vm=0; omission means vm=1.
Zero-extend narrow sources to 2*SEW, subtract the second source from vs2 and keep low 2*SEW bits without accumulating old vd. rs1 first takes low bits when XLEN>SEW or sign-extends to SEW when XLEN<SEW, then zero-extends to 2*SEW; x0 supplies zero. No saturation, vxrm use or vxsat change.
Narrow sources overlap wide vd only with EMUL>=1 and equal highest registers, forcing mask/tail-agnostic behavior. Masked vd excludes v0, which cannot supply mask and data together. Prestart stays unchanged; inactive/tail follow vma/vta, retaining old values or allowing all ones, without guaranteed zeroing.
RV32/RV64 V 1.0; require enabled vector state, vill=0 and support for the selected SEW and 2*SEW; SEW=64 needs additional 128-bit integer elements. Active elements satisfy vstart<=i<vl with masking enabled; vstart>=vl (including vl=0) updates nothing. Implementations may reject nonzero vstart values they cannot produce; success resets vstart=0. The animation fixes LMUL=m1, VLEN=4096, vstart=0; stages are not processor cycles.
VVector Operations
Extension condition: RV32/RV64 V 1.0; require enabled vector state, vill=0 and support for the selected SEW and 2*SEW; SEW=64 requires additional 128-bit integer element support.
Instruction Behavior
vwsubu.vx is a RISC-V V extension vector-scalar unsigned widening subtract instruction. For active elements, the SEW value from vs2 and the SEW value formed from x[rs1] by the .vx rule are zero-extended to 2*SEW, then subtracted and written to the 2*SEW-wide vd destination.
VWSUBU.VX Decode And Execute Animation
Starts from OP-V encoding fields, then shows how VWSUBU zero-extends SEW source elements, subtracts at 2*SEW width, and writes vd.
Instruction input
vwsubu.vx
Teaching context: V 1.0, enabled vector state and valid supported vtype; fix LMUL=m1, VLEN=4096, vstart=0, VLMAX=4096/16. Enter nonnegative bit patterns. Require SEW and 2*SEW support; SEW=64 needs additional 128-bit integer elements beyond baseline V guarantees. Read 16-bit vs2 and a SEW-bit second source; zero-extend narrow sources, subtract the second source from vs2 and keep low 32 bits, without saturation, vxrm use or vxsat change. Equal sources require equal initial values. Wide vd has EMUL=2 and an even start; a narrow source may overlap only its highest register, forcing mask- and tail-agnostic behavior. Scalars first follow XLEN/SEW conversion: take low bits if wider, sign-extend if narrower, then zero-extend to 2*SEW; x0 supplies zero. With v0.t, vd and data sources exclude v0. Only body is shown; inactive/tail follow vma/vta without definite displayed values. VL=0 updates nothing; success resets vstart=0. Stages are teaching steps, not processor cycles.
Execution Context
OP-V encodingvwsubu.vx
funct6
110010
vm
0
vs2
01000
rs1
01011
funct3
110
vd
00100
opcode
1010111
lane
0
1
2
3
4
5
6
7
v8
0x00fa
0x010b
0x011c
0x012d
0x013e
0x014f
0x0160
0x0171
w-
w-
w-
w-
w-
w-
w-
w-
x11
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
0x0013
v0.t
1
0
1
1
1
0
1
1
v4
...
-
...
...
...
-
...
...
Current step
Show OP-V 32-bit encoding fields
vwsubu.vx uses OP-V encoding. The animation places fixed fields, register fields, vm, and the rs1 field in one encoding strip.
This animation shows only ISA-visible relationships from the official V extension: OP-V field decode, active-element reads, 2*SEW widening integer unsigned widening subtraction, mask control, and vd writeback. It does not model pipelines, caches, or timing.
Quick Understanding & Search Notes
VWSUBU.VX is not ordinary SEW-wrapping subtraction: it first zero-extends both source elements, then keeps the subtraction result in a 2*SEW-wide destination element.
Official syntax is `vwsubu.vx vd, vs2, rs1, vm`; vm=1 is unmasked, while vm=0 uses v0.t to select active elements for this instruction.
32-bit OP-V: opcode=1010111, funct6=110010, funct3=110 (OPMVX); vm is bit25, vs2 bits24:20, rs1 bits19:15, vd bits11:7.
For .vx, XLEN>SEW takes the low SEW bits of x[rs1], while XLEN<SEW sign-extends it to SEW; that SEW bit pattern and the SEW vs2 value are then zero-extended to 2*SEW and subtracted.
Destination elements are 2*SEW wide and destination EMUL is twice the source EMUL; this is not an accumulator instruction that reads old vd.
Without a source/destination overlap at different EEWs, tail elements and masked-off elements follow the current vtype tail/mask policy. A legal 2*SEW-destination/SEW-source overlap is mask- and tail-agnostic regardless of vtype; the mnemonic alone does not imply fixed zeroing.
Results wrap at 2*SEW; vd has EMUL=2*LMUL<=8 and wide groups align to their size. Active elements satisfy vstart<=i<vl with masking enabled; prestart stays unchanged, and vstart>=vl (including vl=0) updates no destination elements.
Vector Execution Context
vd has EEW=2*SEW and EMUL=2*LMUL<=8; vs2 is a SEW/LMUL narrow source, and the second source is rs1 converted to SEW. Wide groups align to their size.
32-bit OP-V: opcode=1010111, funct6=110010, funct3=110 (OPMVX); vm bit25, vs2 bits24:20, rs1 bits19:15, vd bits11:7. Optional v0.t means vm=0; omission means vm=1.
Zero-extend narrow sources to 2*SEW, subtract the second source from vs2 and keep low 2*SEW bits without accumulating old vd. rs1 first takes low bits when XLEN>SEW or sign-extends to SEW when XLEN<SEW, then zero-extends to 2*SEW; x0 supplies zero. No saturation, vxrm use or vxsat change.
Narrow sources overlap wide vd only with EMUL>=1 and equal highest registers, forcing mask/tail-agnostic behavior. Masked vd excludes v0, which cannot supply mask and data together. Prestart stays unchanged; inactive/tail follow vma/vta, retaining old values or allowing all ones, without guaranteed zeroing.
RV32/RV64 V 1.0; require enabled vector state, vill=0 and support for the selected SEW and 2*SEW; SEW=64 needs additional 128-bit integer elements. Active elements satisfy vstart<=i<vl with masking enabled; vstart>=vl (including vl=0) updates nothing. Implementations may reject nonzero vstart values they cannot produce; success resets vstart=0. The animation fixes LMUL=m1, VLEN=4096, vstart=0; stages are not processor cycles.
Common Usage Scenarios
Vector Integer Arithmetic
Assume RV32/RV64 V 1.0, enabled vector state, valid supported e16,m1,tu,mu, supported 32-bit results, XLEN=64, VLEN=4096, vl=4, vstart=0, initialized sources, and v0.mask[0..3]=1111. vs2[0]=0, x5=1 → vd[0]=4294967295 (0xffffffff); other active elements follow the same rule and tails retain old values. Success resets vstart=0.
Widening Operations
Assume RV32/RV64 V 1.0, enabled vector state, valid supported e16,m1,tu,mu, supported 32-bit results, XLEN=64, VLEN=4096, vl=4, vstart=0, initialized sources, and v0.mask[0..3]=1111. vs2[0]=0, x5=1 → vd[0]=4294967295 (0xffffffff); other active elements follow the same rule and tails retain old values. Success resets vstart=0.
Vectorized Loops
Assume RV32/RV64 V 1.0, enabled vector state, valid supported e16,m1,tu,mu, supported 32-bit results, XLEN=64, VLEN=4096, vl=4, vstart=0, initialized sources, and v0.mask[0..3]=1111. vs2[0]=0, x5=1 → vd[0]=4294967295 (0xffffffff); other active elements follow the same rule and tails retain old values. Success resets vstart=0.
Pre-Use Checklist
Syntax Check
- vd has EEW=2*SEW and EMUL=2*LMUL<=8; vs2 is a SEW/LMUL narrow source, and the second source is rs1 converted to SEW. Wide groups align to their size.
- 32-bit OP-V: opcode=1010111, funct6=110010, funct3=110 (OPMVX); vm bit25, vs2 bits24:20, rs1 bits19:15, vd bits11:7. Optional v0.t means vm=0; omission means vm=1.
Semantic Check
- Zero-extend narrow sources to 2*SEW, subtract the second source from vs2 and keep low 2*SEW bits without accumulating old vd. rs1 first takes low bits when XLEN>SEW or sign-extends to SEW when XLEN<SEW, then zero-extends to 2*SEW; x0 supplies zero. No saturation, vxrm use or vxsat change.
- Narrow sources overlap wide vd only with EMUL>=1 and equal highest registers, forcing mask/tail-agnostic behavior. Masked vd excludes v0, which cannot supply mask and data together. Prestart stays unchanged; inactive/tail follow vma/vta, retaining old values or allowing all ones, without guaranteed zeroing.
- RV32/RV64 V 1.0; require enabled vector state, vill=0 and support for the selected SEW and 2*SEW; SEW=64 needs additional 128-bit integer elements. Active elements satisfy vstart<=i<vl with masking enabled; vstart>=vl (including vl=0) updates nothing. Implementations may reject nonzero vstart values they cannot produce; success resets vstart=0. The animation fixes LMUL=m1, VLEN=4096, vstart=0; stages are not processor cycles.
Pitfalls / Common Confusions
Non-.w forms widen both SEW source operands before subtraction.
The result is a 2*SEW integer subtraction; it does not use vxrm and does not set vxsat.
The destination group is wider and must satisfy V extension EMUL and overlap constraints.
FAQ
Does VWSUBU.VX read old vd as an accumulator?
No. The result is computed from current source operands and written to vd; .wv/.wx use a wide vs2 source and do not imply accumulation into old vd either.